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Author	SHA1	Message	Date
Clifford Wolf	b1cb4d7871	Added "flatten" pass	2013-04-26 14:40:45 +02:00
Clifford Wolf	8f2d90de4f	Fixed handling of positional module parameters	2013-04-26 14:40:25 +02:00
Clifford Wolf	94744ac7b0	Fixed hierarchy pass for hierarchies of parametric modules	2013-04-26 13:28:15 +02:00
Clifford Wolf	453a29c9f6	Only use sha1 checksums for names of parametric modules when the verbose form is to long	2013-04-26 13:13:58 +02:00
Clifford Wolf	e6dca3445a	Fixed "show -format ..." command line parsing	2013-04-15 11:59:35 +02:00
Clifford Wolf	6626aad29a	Added "submod -name ..." support	2013-04-15 11:58:24 +02:00
Clifford Wolf	e0c408cb4a	Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values	2013-04-13 21:19:10 +02:00
Clifford Wolf	c6198ea5a8	Fixed a bug in opt_const when optimizing 1-bit compares with constants	2013-04-13 21:18:24 +02:00
Clifford Wolf	db10275251	Merge branch 'master' of github.com:cliffordwolf/yosys	2013-04-07 16:42:38 +02:00
Clifford Wolf	32dbf7752d	Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	2013-04-07 16:42:29 +02:00
Clifford Wolf	00a877e09b	Merge pull request #5 from hansiglaser/master ... fsm_export: optionally use binary state encoding as state names instead of s0, s1, ...	2013-04-05 07:04:51 -07:00
Johann Glaser	7ef245aa7d	fsm_export: optionally use binary state encoding as state names instead of ... s0, s1, ...	2013-04-05 15:34:40 +02:00
Clifford Wolf	ab74706338	Merge pull request #4 from hansiglaser/master ... fsm_export: specify KISS filename on command line	2013-04-05 02:30:44 -07:00
Johann Glaser	9714072b28	fsm_export: specify KISS filename on command line	2013-04-05 11:17:49 +02:00
Clifford Wolf	af4444e5b9	Fixed/improved handling of colored wires in show command	2013-04-01 14:58:43 +02:00
Clifford Wolf	32ee794bfb	Added support for @<set-name> in expand select ops (%x, %ci, %co)	2013-04-01 14:58:11 +02:00
Clifford Wolf	5919bf5525	Removed 4096 bytes limit for size of command from script file	2013-04-01 14:38:05 +02:00
Clifford Wolf	3ec9fa4048	Added -color <color> <selection> option to show command	2013-04-01 14:12:17 +02:00
Clifford Wolf	9b1ce98db6	Fixed "select" for "%%" stmt with emty stack	2013-03-31 18:06:27 +02:00
Clifford Wolf	b66e9fb348	Added "script" command	2013-03-31 18:05:31 +02:00
Clifford Wolf	f1a2fd966f	Now only use value from "initial" when no matching "always" block is found	2013-03-31 11:51:12 +02:00
Clifford Wolf	161565be10	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	2013-03-31 11:19:11 +02:00
Clifford Wolf	5640b7d607	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	2013-03-31 11:17:56 +02:00
Clifford Wolf	04843bdcbe	Added k68 (m68k compatible cpu) test case from verilator	2013-03-31 11:00:46 +02:00
Clifford Wolf	88af5b6a16	Improved opt_share for reduce cells	2013-03-29 11:19:21 +01:00
Clifford Wolf	0d48b846ac	Improved opt_share for commutative standard cells	2013-03-29 11:01:26 +01:00
Clifford Wolf	d60fbaf664	Added EXTRA_TARGETS Makefile variable	2013-03-28 16:53:40 +01:00
Clifford Wolf	eff8c68dd9	Improved Makefile: Added ENABLE_* switches	2013-03-28 16:50:50 +01:00
Clifford Wolf	73fba5164f	Implemented TCL support (only via -c option at the moment)	2013-03-28 12:26:17 +01:00
Clifford Wolf	b9870a364e	Improved subcircuit verbose output (added portmapper results)	2013-03-28 11:36:54 +01:00
Clifford Wolf	c46597b697	Fixed svgviewer hacks for builtin files	2013-03-28 10:47:35 +01:00
Clifford Wolf	8edf4f378a	Added proper TECHMAP_FAIL support and added support for the celltype attribute in the map file	2013-03-28 10:12:50 +01:00
Clifford Wolf	7bfc7b61a8	Implemented proper handling of stub placeholder modules	2013-03-28 09:20:10 +01:00
Clifford Wolf	98fcb5daa3	Keep viewport transform stable on reload in yosys-svgviewer	2013-03-27 18:48:38 +01:00
Clifford Wolf	92cf7ae2f7	Added check: only one module for "show" unless format is "ps"	2013-03-27 18:31:42 +01:00
Clifford Wolf	35a02ee81e	Now using SVG and yosys-svgviewer per default in show command	2013-03-27 18:14:16 +01:00
Clifford Wolf	9c401b58a2	Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib	2013-03-27 10:51:15 +01:00
Clifford Wolf	62b9e16f87	Imported svgviewer from qt4.8 ... This is from commit 543486a41963f8d20d9771d2107cdd5a22894bdb in the Qt git repository: git://gitorious.org/qt/qt.git	2013-03-27 06:57:57 +01:00
Clifford Wolf	041c06bd9d	Create nice errors when calling RTLIL::Module::derive() of base class	2013-03-26 19:27:49 +01:00
Clifford Wolf	6a231816fa	Collect parameters in hierarchy -generate (and do nothing with them)	2013-03-26 19:11:53 +01:00
Clifford Wolf	26f2439551	Tiny bugfix in simlib.v	2013-03-26 19:06:28 +01:00
Clifford Wolf	7a99349de4	Improvements and bugfixes for generate blocks with local signals	2013-03-26 11:31:34 +01:00
Clifford Wolf	6a382f2aba	Fixed handling of unconditional generate blocks	2013-03-26 09:44:54 +01:00
Clifford Wolf	227520f94d	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
Clifford Wolf	3737964809	Improved verbose output of subcircuit	2013-03-25 11:08:52 +01:00
Clifford Wolf	0f5378b559	Improved method for finding fsm_expand candidates	2013-03-25 02:24:11 +01:00
Clifford Wolf	4a7d624bef	Added hierarchy -generate command for generating skeletton modules	2013-03-25 02:14:33 +01:00
Clifford Wolf	4bd6f1ee8e	Changed fsm_expand to merge multiplexers more aggressively	2013-03-24 17:59:44 +01:00
Clifford Wolf	d9bc024d29	Renamed hansimem.v test case to mem_arst.v	2013-03-24 15:25:08 +01:00
Clifford Wolf	e1a80b356e	Fixed handling of show -viewer	2013-03-24 15:21:57 +01:00