Sylvain Munaut
add6ab9b2a
ice40: Honor the "dont_touch" attribute in FFSSR pass
...
This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-12-08 22:46:28 +01:00
whitequark
7ff5a9db2d
equiv_opt: pass -D EQUIV when techmapping.
...
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
2018-12-07 17:20:34 +00:00
Olof Kindgren
889297c62a
Only use non-blocking assignments of SB_RAM40_4K for yosys
...
In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.
Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.
This patch will change to use non-blocking assignments only for yosys
2018-12-06 21:45:59 +01:00
whitequark
6e559ee3c7
synth_ice40: split map_gates off fine.
2018-12-06 12:04:39 +00:00
whitequark
d9fa4387c9
synth_ice40: add -noabc option, to use built-in LUT techmapping.
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This should be combined with -relut to get sensible results.
2018-12-05 17:13:46 +00:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
ea4870b126
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
2018-12-05 16:30:37 +00:00
whitequark
1719aa88ac
Extract ice40_unlut pass from ice40_opt.
...
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
2018-12-05 16:30:24 +00:00
Sylvain Munaut
3e5ab50a73
ice40: Add option to only use CE if it'd be use by more than X FFs
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Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2018-11-27 21:50:42 +01:00
Clifford Wolf
51f1bbeeb0
Add iCE40 SB_SPRAM256KA simulation model
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-09-10 11:57:24 +02:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
David Shah
cd65eeb3b3
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
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Signed-off-by: David Shah <davey1576@gmail.com>
2018-07-13 13:09:18 +02:00
Clifford Wolf
57fc8dd582
Add "synth_ice40 -json"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-13 13:35:10 +02:00
Clifford Wolf
83631555dd
Fix ice40_opt for cases where a port is connected to a signal with width != 1
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-11 18:12:42 +02:00
Olof Kindgren
faac2c5595
Avoid mixing module port declaration styles in ice40 cells_sim.v
...
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
2018-05-17 13:54:43 +02:00
Tim 'mithro' Ansell
d6bdefd2e9
Improving vpr output support.
...
* Support output BLIF for Xilinx architectures.
* Support using .names in BLIF for Xilinx architectures.
* Use the same `NO_LUT` define in both `synth_ice40` and
`synth_xilinx`.
2018-04-18 16:55:12 -07:00
Tim 'mithro' Ansell
ca39e493ba
synth_ice40: Rework the vpr blif output slightly.
2018-04-18 16:55:08 -07:00
Clifford Wolf
81a457c4a6
Add "synth_ice40 -nodffe"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-16 20:44:26 +02:00
Larry Doolittle
efaef82f75
Squelch trailing whitespace, including meta-whitespace
2018-03-11 16:03:41 +01:00
Graham Edgecombe
f93e6637aa
Fix port names in SB_IO_OD
2017-12-10 15:33:38 +00:00
Graham Edgecombe
52ace35a73
Remove trailing comma from SB_IO_OD port list
...
This isn't compatible with Icarus Verilog.
2017-12-10 15:33:38 +00:00
Tim Ansell
3cc31f197c
Fix spelling in -vpr help for synth_ice40
2017-12-08 18:44:45 -08:00
David Shah
5e8d1922a4
Add remaining UltraPlus cells to ice40 techlib
2017-11-28 11:07:49 +00:00
David Shah
0505f1043c
Remove unnecessary keep attributes
2017-11-18 17:53:21 +00:00
David Shah
8ae73e60e2
Merge branch 'master' into up5k
2017-11-17 15:15:39 +00:00
Clifford Wolf
234726c655
Add "synth_ice40 -vpr"
2017-11-16 21:37:02 +01:00
David Shah
f9f3ca5da0
Add some UltraPlus cells to ice40 techlib
2017-11-16 12:24:35 +00:00
Clifford Wolf
e64b9d5a4d
Fix synth_ice40 doc regarding -top default
2017-09-29 17:52:57 +02:00
Clifford Wolf
81bdf0ad0f
iCE40 flow is not experimental anymore
2016-11-01 11:32:02 +01:00
Clifford Wolf
21659847a7
Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations
2016-07-08 14:41:36 +02:00
Clifford Wolf
df5ebfa0a0
Improved ice40_ffinit error reporting
2016-06-30 09:58:13 +02:00
Clifford Wolf
ca91bccb6b
Added "deminout"
2016-06-19 13:08:16 +02:00
Clifford Wolf
6fe3d5a1cf
Added synth_ice40 support for latches via logic loops
2016-05-06 23:02:37 +02:00
Clifford Wolf
126da0ad3d
Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
2016-05-06 14:32:32 +02:00
Clifford Wolf
a24021ea20
Converted synth_greenpak4 to ScriptPass
2016-04-23 10:27:33 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
2553319081
Added ScriptPass helper class for script-like passes
2016-03-31 11:16:34 +02:00
Clifford Wolf
ec93680bd5
Renamed opt_share to opt_merge
2016-03-31 08:52:49 +02:00
Clifford Wolf
1d0f0d668a
Renamed opt_const to opt_expr
2016-03-31 08:46:56 +02:00
Clifford Wolf
0ccfb88728
Work around DDR dout sim glitches in ice40 SB_IO sim model
2016-02-07 11:19:48 +01:00
Clifford Wolf
d69395ca08
Added dffsr2dff
2016-02-02 17:19:01 +01:00
Clifford Wolf
2ee608246f
Re-run ice40_opt in "synth_ice40 -abc2"
2015-12-22 12:19:11 +01:00
Clifford Wolf
3102ffbb83
Improvements in ice40_opt
2015-12-22 12:18:38 +01:00
Clifford Wolf
8bf452c364
Bugfix in ice40_ffinit
2015-12-22 12:18:06 +01:00
Clifford Wolf
ec93d258a4
Improved ice40_ffinit
2015-12-22 11:15:25 +01:00
Clifford Wolf
494e5f24f9
Added "synth_ice40 -abc2"
2015-12-08 11:16:26 +01:00
Clifford Wolf
4d0a6dac7b
Merge pull request #108 from cseed/master
...
Added LO to ICESTORM_LC for LUT cascade route.
2015-12-07 03:32:20 +01:00
Cotton Seed
9f5b6e4cbc
Added LO to ICESTORM_LC for LUT cascade route.
2015-12-06 17:24:48 -05:00
Clifford Wolf
0793f1b196
Added ice40_ffinit pass
2015-11-26 18:11:06 +01:00
Clifford Wolf
8ff229a3ea
Fixed WE/RE usage in iCE40 BRAM mapping
2015-11-24 10:51:34 +01:00
