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Code Activity
yosys/techlibs/ice40
History
whitequark 45cb6200af opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
..
tests Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
.gitignore Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
arith_map.v Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_init.py Switched to Python 3 2015-08-22 09:59:33 +02:00
brams_map.v Fixed WE/RE usage in iCE40 BRAM mapping 2015-11-24 10:51:34 +01:00
cells_map.v Improving vpr output support. 2018-04-18 16:55:12 -07:00
cells_sim.v Add iCE40 SB_SPRAM256KA simulation model 2018-09-10 11:57:24 +02:00
ice40_ffinit.cc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
ice40_ffssr.cc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
ice40_opt.cc Extract ice40_unlut pass from ice40_opt. 2018-12-05 16:30:24 +00:00
ice40_unlut.cc Extract ice40_unlut pass from ice40_opt. 2018-12-05 16:30:24 +00:00
latches_map.v Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Makefile.inc Extract ice40_unlut pass from ice40_opt. 2018-12-05 16:30:24 +00:00
synth_ice40.cc opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. 2018-12-05 16:30:37 +00:00