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Author SHA1 Message Date
whitequark
48655dfb8b proc_mux: consider \src attribute on CaseRule. 2019-07-08 13:18:18 +00:00
whitequark
55c1f40277 verilog_backend: dump attributes on CaseRule, as comments. 
Attributes are not permitted in that position by Verilog grammar.
 2019-07-08 12:48:50 +00:00
whitequark
b1f400aeb8 genrtlil: emit \src attribute on CaseRule. 2019-07-08 12:29:08 +00:00
whitequark
93bc5affd3 Allow attributes on individual switch cases in RTLIL. 
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
 2019-07-08 11:34:58 +00:00
Clifford Wolf
030483ffb9
Merge pull request #1159 from btut/fix/1090_segfault_cell_and_wire 
Throw runtime exception when trying to convert inexistend C++ object to Python
 2019-07-05 11:57:41 +02:00
Benedikt Tutzer
3a1a41bdb1 Throw runtime exception when trying to convert a c++-pointer to a 
python-object in case the pointer is a nullptr to avoid a segfault.

Fixes #1090
 2019-07-04 14:20:13 +02:00
Eddie Hung
de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell 
write_xaiger to treat unknown cell connections as keep-s
 2019-07-03 09:43:00 -07:00
Clifford Wolf
e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144 
Improve specify dummy parser
 2019-07-03 12:30:37 +02:00
Clifford Wolf
1f173210eb Fix tests/various/specify.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:25:05 +02:00
Clifford Wolf
ba36567908 Some cleanups in "ignore specify parser" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-03 11:22:10 +02:00
Clifford Wolf
224ad8fe33
Merge pull request #1154 from whitequark/manual-sync-always 
manual: explain the purpose of `sync always`
 2019-07-03 10:45:29 +02:00
Eddie Hung
10524064e9 write_xaiger to treat unknown cell connections as keep-s 2019-07-02 19:14:30 -07:00
Eddie Hung
9c556e3c02 Add test 2019-07-02 19:13:40 -07:00
Eddie Hung
8455d1f4ff
Merge pull request #1150 from YosysHQ/eddie/script_from_wire 
Add "script -select [selection]" to allow commands to be taken from wires
 2019-07-02 10:20:42 -07:00
whitequark
9251c000e8 manual: explain the purpose of sync always. 2019-07-02 17:10:13 +00:00
David Shah
0447794c51
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux 
memory_dff: Fix checking of feedback mux input when more than one mux
 2019-07-02 16:47:54 +01:00
Eddie Hung
81a717e9b7 Update test for Pass::call_on_module() 2019-07-02 08:22:31 -07:00
Eddie Hung
f1504696e5 Use Pass::call_on_module() as per @cliffordwolf comments 2019-07-02 08:20:37 -07:00
Eddie Hung
90382a0f6d Update test too 2019-07-02 08:19:23 -07:00
Eddie Hung
02ba85b133 script -select -> script -scriptwire 2019-07-02 08:17:26 -07:00
David Shah
d45936fe5f memory_dff: Fix checking of feedback mux input when more than one mux 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-02 13:35:50 +01:00
Clifford Wolf
d206eca03b Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-02 11:36:26 +02:00
Eddie Hung
6282a67332 Space 2019-07-01 11:59:10 -07:00
Eddie Hung
9018f29d54 Move CHANGELOG entry from yosys-0.8 to 0.9 2019-07-01 09:46:56 -07:00
Eddie Hung
dda2ec3cc5 Merge branch 'master' into eddie/script_from_wire 2019-07-01 09:46:32 -07:00
Eddie Hung
0067dc44f3 Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG 2019-07-01 09:44:53 -07:00
Eddie Hung
7be8551c8d Merge branch 'master' of github.com:YosysHQ/yosys 2019-07-01 09:43:33 -07:00
Eddie Hung
04459cb30a Comment out invalid syntax 2019-06-30 11:48:01 -07:00
Eddie Hung
dd8d264bf5 install *_nowide.lut files 2019-06-29 19:37:04 -07:00
Eddie Hung
c5563b67c8
Merge pull request #1149 from gsomlo/gls-1098-abcext-fixup 
Make abc9 pass aware of optional ABCEXTERNAL override
 2019-06-28 15:02:50 -07:00
Eddie Hung
fd2fb4f0f0 Merge branch 'master' into eddie/script_from_wire 2019-06-28 14:56:34 -07:00
Eddie Hung
0ec7c09756 autotest.sh to define _AUTOTB when test_autotb 2019-06-28 14:56:22 -07:00
Eddie Hung
64f6b0c747 Try command in another module 2019-06-28 13:41:32 -07:00
Eddie Hung
4e1a4927e2 Add to CHANGELOG 2019-06-28 13:39:06 -07:00
Eddie Hung
06971385fa Support ability for "script -select" to take commands from wires 2019-06-28 13:36:33 -07:00
Eddie Hung
2c6aaef3db Add test 2019-06-28 13:32:09 -07:00
Eddie Hung
b3f162e94e Replace log_assert() with meaningful log_error() 2019-06-28 12:54:44 -07:00
Eddie Hung
728839d6ca Remove peepopt call in synth_xilinx since already in synth -run coarse 2019-06-28 12:53:38 -07:00
Gabriel L. Somlo
8cb3655ecd Make abc9 pass aware of optional ABCEXTERNAL override 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-28 14:56:16 -04:00
Eddie Hung
b5f1bd0df1 Add missing CHANGELOG entries 2019-06-28 11:16:15 -07:00
Eddie Hung
4a2a93aa06 Fix spacing 2019-06-28 11:10:36 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig 
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 2019-06-28 10:59:03 -07:00
Eddie Hung
dc677c791d Add test from #1144, and try reading without '-specify' flag 2019-06-28 10:12:48 -07:00
Eddie Hung
38d8806bd7 Add generic __builtin_bswap32 function 2019-06-28 09:59:47 -07:00
Eddie Hung
524af21317 Also fix write_aiger for UB 2019-06-28 09:55:07 -07:00
Eddie Hung
36e2eb06bb Fix more potential for undefined behaviour due to container invalidation 2019-06-28 09:51:43 -07:00
Eddie Hung
03705f69f4 Update synth_ice40 -device doc to be relevant for -abc9 only 2019-06-28 09:49:01 -07:00
Eddie Hung
3f87575cb6 Disable boxing of ECP5 dist RAM due to regression 2019-06-28 09:46:36 -07:00
Eddie Hung
0318860b93 Add write address to abc_scc_break of ECP5 dist RAM 2019-06-28 09:45:48 -07:00
Eddie Hung
b9ddee0c87 Fix DO4 typo 2019-06-28 09:45:40 -07:00