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Author	SHA1	Message	Date
Clifford Wolf	44f13aff92	Improved seeding of color rng in show command	2014-07-18 16:44:45 +02:00
Clifford Wolf	a341931972	Only create collision detect logic in memory_share if necessary	2014-07-18 14:32:40 +02:00
Clifford Wolf	ddb01df42e	Bugfix in tests/memories/run-test.sh	2014-07-18 13:45:25 +02:00
Clifford Wolf	5d9127418b	added tests/memories	2014-07-18 13:25:19 +02:00
Clifford Wolf	ab4b26679f	Added memory_share	2014-07-18 13:16:56 +02:00
Clifford Wolf	a721f7d768	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	2014-07-18 11:36:34 +02:00
Clifford Wolf	309ae98246	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	2014-07-18 10:28:45 +02:00
Clifford Wolf	2d69c309f9	Added function-like cell creation helpers	2014-07-18 10:27:06 +02:00
Clifford Wolf	a8cedb2257	Added log_id() helper function	2014-07-18 10:26:01 +02:00
Clifford Wolf	ec3a798194	Also simulate unmapped memories in "make test"	2014-07-17 16:53:52 +02:00
Clifford Wolf	9b183539af	Implemented dynamic bit-/part-select for memory writes	2014-07-17 16:49:23 +02:00
Clifford Wolf	f1ca93a0a3	Fixed simlib.v model for $mem	2014-07-17 16:48:36 +02:00
Clifford Wolf	5867f6bcdc	Added support for bit/part select to mem2reg rewriter	2014-07-17 13:49:32 +02:00
Clifford Wolf	6d69d4aaa8	Added support for constant bit- or part-select for memory writes	2014-07-17 13:13:21 +02:00
Clifford Wolf	1b00861d0a	Improved opt_reduce handling of mem wr_en mux bits	2014-07-17 12:12:04 +02:00
Clifford Wolf	274c514879	Fixed RTLIL::SigSpec::append_bit() for appending constants	2014-07-17 12:10:57 +02:00
Clifford Wolf	b76bf05cda	Added support for "blackbox" attribute to iopadmap	2014-07-17 08:59:07 +02:00
Clifford Wolf	64a6906cc4	Added support for "blackbox" attribute to flatten/techmap	2014-07-17 08:58:51 +02:00
Clifford Wolf	b171a4c1bc	Added "inout" ports support to read_liberty	2014-07-16 18:12:46 +02:00
Clifford Wolf	5057935722	Set blackbox attribute in "read_liberty -lib"	2014-07-16 18:12:16 +02:00
Clifford Wolf	24f58e57f3	Fixed spelling of "direction" in read_liberty messages	2014-07-16 18:02:28 +02:00
Clifford Wolf	02346cd1d5	Merged new $mem/$memwr WR_EN interface	2014-07-16 14:15:33 +02:00
Clifford Wolf	73a345294a	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	2014-07-16 14:08:51 +02:00
Clifford Wolf	d678b6533d	improved opt_reduce for $mem/$memwr WR_EN multiplexers	2014-07-16 14:08:51 +02:00
Clifford Wolf	543551b80a	changes in verilog frontend for new $mem/$memwr WR_EN interface	2014-07-16 12:49:50 +02:00
Clifford Wolf	765f172211	Changes to "memory" pass for new $memwr/$mem WR_EN interface	2014-07-16 12:49:50 +02:00
Clifford Wolf	dcdd5c11b4	Updated simlib to new $mem/$memwr interface	2014-07-16 11:46:40 +02:00
Clifford Wolf	73e0e13d2f	Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal	2014-07-16 11:38:02 +02:00
Clifford Wolf	964a67ac41	Added note to "make test": use git checkout of iverilog	2014-07-16 10:03:07 +02:00
Clifford Wolf	0f9ca49dc6	Added passing of various options to vhdl2verilog	2014-07-12 10:02:39 +02:00
Clifford Wolf	847e2ee4a1	Use "verilog -sv" to parse .sv files	2014-07-11 13:10:51 +02:00
Clifford Wolf	55a1b8dbac	Fixed processing of initial values for block-local variables	2014-07-11 13:05:53 +02:00
Clifford Wolf	3b52121d32	now ignore init attributes on non-register wires in sat command	2014-07-05 11:18:38 +02:00
Clifford Wolf	ee8ad72fd9	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
Clifford Wolf	1c81ab49e7	small changes in presentation	2014-07-02 06:16:31 +02:00
Clifford Wolf	d26561cc44	Tiny fix in presentation	2014-06-29 09:27:03 +02:00
Clifford Wolf	3a3f5d5923	Progress in presentation	2014-06-29 09:14:49 +02:00
Clifford Wolf	89c85cac41	Added links to some liberty files to README	2014-06-28 12:11:42 +02:00
Clifford Wolf	3e96ce8680	Progress in presentation	2014-06-26 22:05:39 +02:00
Clifford Wolf	076182c34e	Fixed handling of mixed real/int ternary expressions	2014-06-25 10:05:36 +02:00
Clifford Wolf	4fc43d1932	More found_real-related fixes to AstNode::detectSignWidthWorker	2014-06-24 15:08:48 +02:00
Clifford Wolf	a7aea17959	Progress in presentation	2014-06-22 12:50:29 +02:00
Clifford Wolf	3345fa0bab	Little steps in realmath test bench	2014-06-21 21:43:04 +02:00
Clifford Wolf	65b2e9c064	fixed signdness detection for expressions with reals	2014-06-21 21:41:13 +02:00
Clifford Wolf	072604f30f	fixed typo	2014-06-21 21:13:18 +02:00
Clifford Wolf	b18fa95d2f	Progress in presentation	2014-06-21 16:33:33 +02:00
Clifford Wolf	1c85584fe5	Do not create $dffsr cells with no-op resets in proc_dff	2014-06-19 12:29:29 +02:00
Clifford Wolf	df76da8fd7	Added test case for AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:49:59 +02:00
Clifford Wolf	80e4594695	Added AstNode::MEM2REG_FL_CMPLX_LHS	2014-06-17 21:39:25 +02:00
Clifford Wolf	798ff88855	Improved handling of relational op of real values	2014-06-17 12:47:51 +02:00