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Author	SHA1	Message	Date
Clifford Wolf	b515fd2d25	Add peepopt_muldiv, fixes #930 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-30 11:25:15 +02:00
Clifford Wolf	4306bebe58	pmgen progress ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-30 10:51:51 +02:00
Clifford Wolf	d2d402e625	Run "peepopt" in generic "synth" pass and "synth_ice40" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-30 08:10:37 +02:00
Clifford Wolf	bb4f3642de	Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-30 08:04:22 +02:00
Clifford Wolf	58238da133	Progress in shiftmul peepopt pattern ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-30 07:59:39 +02:00
Clifford Wolf	314ff1e4ca	Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef ... Add -undef option to equiv_opt, passed to equiv_induct	2019-04-29 13:54:26 +02:00
Clifford Wolf	8fde245ea2	Merge pull request #967 from olegendo/depfile_esc_spaces ... escape spaces with backslash when writing dep file	2019-04-29 13:48:52 +02:00
Clifford Wolf	ea547bcaa3	Add "peepopt" skeleton ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-29 13:38:56 +02:00
Clifford Wolf	9f792c599d	Add pmgen support for multiple patterns in one matcher ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-29 13:02:05 +02:00
Oleg Endo	4f15e7f00f	fix codestyle formatting	2019-04-29 19:20:33 +09:00
Clifford Wolf	32881a989c	Support multiple pmg files (right now just concatenated together) ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-29 12:09:02 +02:00
Oleg Endo	e531fb203a	escape spaces with backslash when writing dep file ... filenames are sparated by spaces in the dep file. if a filename in the dep file contains spaces they must be escaped, otherwise the tool that reads the dep file will see multiple wrong filenames.	2019-04-29 16:13:34 +09:00
Clifford Wolf	754b1ee4b3	Drive dangling wires with init attr with their init value, fixes #956	2019-04-29 08:44:53 +02:00
Eddie Hung	acafcdc94d	Copy with 1'bx padding in $shiftx	2019-04-28 13:04:34 -07:00
Eddie Hung	e97178a888	WIP	2019-04-28 12:51:00 -07:00
Eddie Hung	af840bbc63	Move neg-pol to pos-pol mapping from ff_map to cells_map.v	2019-04-28 12:36:04 -07:00
Eddie Hung	d855683917	Revert synth_xilinx 'fine' label more to how it used to be...	2019-04-26 16:53:16 -07:00
Eddie Hung	ea0e0722bb	Where did this check come from!?!	2019-04-26 15:35:34 -07:00
Eddie Hung	727eec04c5	Refactor synth_xilinx to auto-generate doc	2019-04-26 14:32:18 -07:00
Eddie Hung	1ea6d7920f	Cleanup ice40	2019-04-26 14:31:59 -07:00
Eddie Hung	159e7cc298	Add -undef option to equiv_opt, passed to equiv_induct	2019-04-26 11:16:48 -07:00
Eddie Hung	408161ea3a	Misspelling	2019-04-25 16:46:13 -07:00
Clifford Wolf	67005633e2	Add specify support to README ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 23:01:38 +02:00
Clifford Wolf	64925b4e8f	Improve $specrule interface ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 22:57:10 +02:00
Clifford Wolf	4575e4ad86	Improve $specrule interface ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 22:18:04 +02:00
Clifford Wolf	71c38d9de5	Add $specrule cells for $setup/$hold/$skew specify rules ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	634482380c	Preserve $specify[23] cells ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	012c6af088	Allow $specify[23] cells in blackbox modules ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	e807e88b60	Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	846eb5ea98	Add $specify2/$specify3 support to write_verilog ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	0bf9d0087c	Add support for $assert/$assume/$cover to write_verilog ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	aec2475a9d	Add CellTypes support for $specify2 and $specify3 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	e1d73e03d3	Add InternalCellChecker support for $specify2 and $specify3 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	b232e027bf	Checking and fixing specify cells in genRTLIL ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	41b843c27b	Un-break default specify parser ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	3cc95fb4be	Add specify parser ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	a7e11261bd	Add $specify2 and $specify3 cells to simlib ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	b2020ab44f	Merge pull request #957 from YosysHQ/oai4fix ... Fixes for OAI4 cell implementation	2019-04-23 19:59:39 +02:00
David Shah	742c2f245d	Fixes for OAI4 cell implementation ... Fixes #955 and the underlying issue in #954 Signed-off-by: David Shah <dave@ds0.me>	2019-04-23 17:54:00 +01:00
Eddie Hung	c6156f3118	Format some names using inline code	2019-04-23 09:01:10 -07:00
Eddie Hung	f66792c43a	Fix spelling	2019-04-23 08:58:34 -07:00
Clifford Wolf	c84cdc711c	Remove some left-over log_dump() ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 17:55:41 +02:00
Eddie Hung	d9daf09cf3	Merge pull request #914 from YosysHQ/xc7srl ... synth_xilinx to now infer SRL16E/SRLC32E	2019-04-22 13:31:30 -07:00
Eddie Hung	ec88129a5c	Update help message	2019-04-22 11:38:23 -07:00
Clifford Wolf	bc98a463a4	Merge pull request #952 from YosysHQ/clifford/fix370 ... Determine correct signedness and expression width in for-loop unrolling	2019-04-22 20:10:46 +02:00
Clifford Wolf	8ed4a53d99	Merge pull request #951 from YosysHQ/clifford/logdebug ... Add log_debug() framework	2019-04-22 20:09:51 +02:00
Clifford Wolf	1d538ff1ec	Merge pull request #949 from YosysHQ/clifford/pmux2shimprove ... Add full_pmux feature to pmux2shiftx	2019-04-22 20:01:43 +02:00
Clifford Wolf	3be5aac52c	Merge pull request #953 from YosysHQ/clifford/fix948 ... Add support for zero-width signals to Verilog back-end	2019-04-22 20:01:09 +02:00
Eddie Hung	0e76718720	Move 'shregmap -tech xilinx' into map_cells	2019-04-22 10:45:39 -07:00
Clifford Wolf	0e0c80fac8	Add support for zero-width signals to Verilog back-end, fixes #948 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-22 19:44:42 +02:00