Eddie Hung
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0f1a4cc03c
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verific_import() changes to avoid ElaborateAll()
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2019-05-03 20:53:25 +02:00 |
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Clifford Wolf
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373b236108
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Merge pull request #969 from YosysHQ/clifford/pmgenstuff
Improve pmgen, Add "peepopt" pass with shift-mul pattern
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2019-05-03 20:39:50 +02:00 |
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Clifford Wolf
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f170fb6383
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Merge pull request #984 from YosysHQ/eddie/fix_982
dffinit to do nothing when (* init *) value is 1'bx
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2019-05-03 20:34:32 +02:00 |
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Eddie Hung
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1d43a25f08
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Revert "synth_xilinx to call dffinit with -noreinit"
This reverts commit 1f62dc9081.
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2019-05-03 09:55:02 -07:00 |
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Eddie Hung
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e08df0c739
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If init is 1'bx, do not add to dict as per @cliffordwolf
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2019-05-03 08:06:16 -07:00 |
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Eddie Hung
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fc349de033
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Revert "dffinit -noreinit to silently continue when init value is 1'bx"
This reverts commit aa081f83c7.
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2019-05-03 08:05:37 -07:00 |
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Clifford Wolf
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71ede7cb05
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Merge pull request #976 from YosysHQ/clifford/fix974
Fix width detection of memory access with bit slice
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2019-05-03 15:29:44 +02:00 |
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Clifford Wolf
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97423cadda
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Merge pull request #985 from YosysHQ/clifford/fix981
Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires
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2019-05-03 15:25:46 +02:00 |
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Clifford Wolf
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d2aa123226
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Fix typo in tests/svinterfaces/runone.sh
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 14:40:51 +02:00 |
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Clifford Wolf
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537b90ee88
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Merge pull request #979 from jakobwenzel/svinterfacesTestcase
fail svinterfaces testcases on yosys error exit
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2019-05-03 14:37:46 +02:00 |
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Clifford Wolf
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42190207b4
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Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 14:25:01 +02:00 |
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Clifford Wolf
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5c2c0b4bb2
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Further improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 09:22:26 +02:00 |
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Clifford Wolf
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f12e1155f1
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Improve unused-detection for opt_clean driver-driver conflict warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 09:12:10 +02:00 |
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Clifford Wolf
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2b29aa5c86
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Update pmgen documentation
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:35:45 +02:00 |
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Clifford Wolf
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e8c5afcb84
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Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-03 08:25:30 +02:00 |
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Eddie Hung
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1f62dc9081
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synth_xilinx to call dffinit with -noreinit
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2019-05-02 17:41:20 -07:00 |
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Eddie Hung
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aa081f83c7
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dffinit -noreinit to silently continue when init value is 1'bx
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2019-05-02 17:40:39 -07:00 |
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Jim Lawson
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509f729e55
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Merge remote-tracking branch 'upstream/master'
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2019-05-02 07:59:07 -07:00 |
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Jakob Wenzel
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98ffe5fb00
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fail svinterfaces testcases on yosys error exit
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2019-05-02 09:52:30 +02:00 |
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Clifford Wolf
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98925f6c4b
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Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine
Revert synth_xilinx 'fine' label more to how it used to be...
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2019-05-02 09:11:07 +02:00 |
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Eddie Hung
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485bf372e7
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Merge pull request #978 from ucb-bar/fmtfirrtl
Re-indent firrtl.cc:struct memory - no functional change.
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2019-05-01 18:24:21 -07:00 |
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Eddie Hung
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d394b9301b
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Back to passing all xc7srl tests!
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2019-05-01 18:23:21 -07:00 |
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Eddie Hung
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31ff0d8ef5
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Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
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2019-05-01 18:09:38 -07:00 |
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Eddie Hung
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f86d153cef
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Merge branch 'master' of github.com:YosysHQ/yosys
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2019-05-01 16:26:43 -07:00 |
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Jim Lawson
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6ea09caf01
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Re-indent firrtl.cc:struct memory - no functional change.
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2019-05-01 16:21:13 -07:00 |
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Jim Lawson
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6c361bb198
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Merge remote-tracking branch 'upstream/master'
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2019-05-01 16:13:11 -07:00 |
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Clifford Wolf
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7a0af004a0
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Merge branch 'clifford/fix883'
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2019-05-02 00:04:12 +02:00 |
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Clifford Wolf
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521663f09e
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Add missing enable_undef to "sat -tempinduct-def", fixes #883
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-02 00:03:31 +02:00 |
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Clifford Wolf
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e8a157b47c
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Merge pull request #977 from ucb-bar/fixfirrtlmem
Fix #938 - Crash occurs in case when use write_firrtl command
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2019-05-01 23:47:16 +02:00 |
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Jim Lawson
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38f5424f92
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Fix #938 - Crash occurs in case when use write_firrtl command
Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
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2019-05-01 13:16:01 -07:00 |
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Clifford Wolf
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93b7fd7744
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Fix floating point exception in qwp, fixes #923
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 15:06:46 +02:00 |
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Clifford Wolf
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6bbe2fdbf3
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Add splitcmplxassign test case and silence splitcmplxassign warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 10:01:54 +02:00 |
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Clifford Wolf
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3b6a02d3a7
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Fix width detection of memory access with bit slice, fixes #974
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 09:57:26 +02:00 |
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Clifford Wolf
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e5cb9435a0
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Add additional test cases for for-loops
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 09:32:07 +02:00 |
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Clifford Wolf
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a30b99e66e
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Silently resolve completely unused cell-vs-const driver-driver conflicts
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 09:29:34 +02:00 |
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Clifford Wolf
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59d74a3348
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Re-enable "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-01 09:02:39 +02:00 |
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Clifford Wolf
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32ff37bb5a
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Fix segfault in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 22:20:45 +02:00 |
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Jim Lawson
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58650ffe87
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Merge remote-tracking branch 'upstream/master'
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2019-04-30 13:19:27 -07:00 |
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Clifford Wolf
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e35fe1344d
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Disabled "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 20:22:50 +02:00 |
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Clifford Wolf
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9c7d23446d
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Merge pull request #972 from YosysHQ/clifford/fix968
Add final loop variable assignment when unrolling for-loops
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2019-04-30 18:09:44 +02:00 |
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Clifford Wolf
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a27eeff573
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Merge pull request #966 from YosysHQ/clifford/fix956
Drive dangling wires with init attr with their init value
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2019-04-30 18:08:41 +02:00 |
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Clifford Wolf
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5bc4de077a
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Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx
Refactor synth_xilinx to auto-generate doc
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2019-04-30 18:07:19 +02:00 |
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Clifford Wolf
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d9d50b0b0c
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Merge branch 'master' into eddie/refactor_synth_xilinx
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2019-04-30 17:00:34 +02:00 |
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Clifford Wolf
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58e991a0eb
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Merge pull request #973 from christian-krieg/feature/python_bindings
Feature/python bindings cleanup
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2019-04-30 15:48:42 +02:00 |
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Clifford Wolf
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84f3a796e1
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Include filename in "Executing Verilog-2005 frontend" message, fixes #959
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 15:37:46 +02:00 |
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Clifford Wolf
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9268cd1613
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Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 15:19:10 +02:00 |
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Clifford Wolf
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9af825e31e
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Add final loop variable assignment when unrolling for-loops, fixes #968
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 15:03:32 +02:00 |
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Clifford Wolf
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9d117eba9d
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Add handling of init attributes in "opt_expr -undriven"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-04-30 14:46:12 +02:00 |
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Benedikt Tutzer
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dc06e3a28b
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Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_bindings
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2019-04-30 13:22:33 +02:00 |
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Benedikt Tutzer
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124a284487
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Cleaned up root directory
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2019-04-30 13:19:04 +02:00 |
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