453 commits

Author	SHA1	Message	Date
Clifford Wolf	cdd6e11af5	Added support for blanks after -I and -D in read_verilog	2014-02-02 13:06:21 +01:00
Clifford Wolf	d06258f74f	Added constant size expression support of sized constants	2014-02-01 13:50:23 +01:00
Clifford Wolf	375c4dddc1	Added read_verilog -icells option	2014-01-29 00:59:28 +01:00
Clifford Wolf	0b47d907d3	Fixed handling of unsized constants in verilog frontend	2014-01-24 15:05:24 +01:00
Clifford Wolf	9a1eb45c75	Added Verilog parser support for asserts	2014-01-19 04:18:22 +01:00
Clifford Wolf	13359d65ba	Fixed parsing of verilog macros at end of line	2014-01-18 19:22:20 +01:00
Clifford Wolf	6170cfe9cd	Added verilog_defaults command	2014-01-17 17:22:29 +01:00
Clifford Wolf	1dcbba1abf	Fixed parsing of non-arg macro calls followed by "("	2013-12-27 16:25:27 +01:00
Clifford Wolf	72026a934e	Fixed parsing of macros with no arguments and expansion text starting with "("	2013-12-27 15:05:52 +01:00
Clifford Wolf	ecc30255ba	Added proper === and !== support in constant expressions	2013-12-27 13:50:08 +01:00
Clifford Wolf	fbd06a1afc	Added elsif preproc support	2013-12-18 13:41:36 +01:00
Clifford Wolf	921064c200	Added support for macro arguments	2013-12-18 13:21:02 +01:00
Clifford Wolf	5c39948ead	Added AstNode::mkconst_str API	2013-12-05 12:53:49 +01:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	507c63d112	Added support for local regs in named blocks	2013-12-04 09:10:16 +01:00
Clifford Wolf	7d9a90396d	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
Clifford Wolf	1de12e1efc	Improved handling of initialized registers	2013-11-23 16:26:59 +01:00
Clifford Wolf	295e352ba6	Renamed "placeholder" to "blackbox"	2013-11-22 15:01:12 +01:00
Clifford Wolf	a362fd81ae	Fixed O(n^2) performance bug in verilog preprocessor	2013-11-22 14:08:43 +01:00
Clifford Wolf	e4429c480e	Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)	2013-11-22 12:46:02 +01:00
Clifford Wolf	92035fb38e	Implemented indexed part selects	2013-11-20 13:05:27 +01:00
Clifford Wolf	0f04738f40	Added "synthesis" in (synopsys|synthesis) comment support	2013-11-20 11:44:09 +01:00
Clifford Wolf	19dba2561e	Implemented part/bit select on memory read	2013-11-20 10:51:32 +01:00
Clifford Wolf	e340532ce5	Added init= attribute for fpga-style reset values	2013-11-20 01:49:37 +01:00
Clifford Wolf	0dfdbd991a	Fixed parsing of module arguments when one type is used for many args	2013-11-19 20:35:31 +01:00
Clifford Wolf	63060dcd2e	Fixed parsing of "parameter integer"	2013-11-13 15:30:23 +01:00
Clifford Wolf	f050c40519	Various fixes for correct parameter support	2013-11-07 10:02:11 +01:00
Clifford Wolf	23cf23418c	Fixed handling of boolean attributes (frontends)	2013-10-24 11:20:13 +02:00
Clifford Wolf	eae43e2db4	Fixed handling of boolean attributes (kernel)	2013-10-24 10:59:27 +02:00
Johann Glaser	f352205635	fixed Verilog parser filename and line numbering issue with include files	2013-08-21 09:20:59 +02:00
Johann Glaser	a99c224157	Added support for include directories with the new '-I' argument of the ... 'read_verilog' command	2013-08-20 15:48:16 +02:00
Johann Glaser	6c4cbc03c2	Added support for notif0/notif1 primitives	2013-08-20 11:23:59 +02:00
Clifford Wolf	8656b1c08f	Added support for bufif0/bufif1 primitives	2013-08-19 19:50:04 +02:00
Clifford Wolf	4214561890	Improved ast dumping (ast/verilog frontend)	2013-08-19 19:49:14 +02:00
Clifford Wolf	00a6c1d9a5	Major redesign of expr width/sign detecion (verilog/ast frontend)	2013-07-09 14:31:57 +02:00
Clifford Wolf	56432a920f	Added defparam support to Verilog/AST frontend	2013-07-04 14:12:33 +02:00
Clifford Wolf	0c6ffc4c65	More fixes for bugs found using xsthammer	2013-06-13 11:18:45 +02:00
Clifford Wolf	4b311b7b99	Further improved and extended xsthammer	2013-06-11 19:49:35 +02:00
Clifford Wolf	db98a18edb	Enabled AST/Verilog front-end optimizations per default	2013-06-10 13:19:04 +02:00
Clifford Wolf	46fbe9d262	Added SAT generator and simple sat_solve command	2013-06-07 13:59:13 +02:00
Johann Glaser	10a195c0a1	added option '-Dname[=definition]' to command 'read_verilog'	2013-05-19 17:07:52 +02:00
Clifford Wolf	b56e06d2f5	Added support for verilog === operator	2013-05-07 14:35:40 +02:00
Clifford Wolf	161565be10	Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)	2013-03-31 11:19:11 +02:00
Clifford Wolf	7bfc7b61a8	Implemented proper handling of stub placeholder modules	2013-03-28 09:20:10 +01:00
Clifford Wolf	7a99349de4	Improvements and bugfixes for generate blocks with local signals	2013-03-26 11:31:34 +01:00
Clifford Wolf	df9753d398	Added mem2reg option to verilog frontend	2013-03-24 11:13:32 +01:00
Clifford Wolf	e45d1c8865	Tiny fixes to verilog parser	2013-03-23 18:54:31 +01:00
Clifford Wolf	8a6b0a3520	Added help messages to ilang and verilog frontends	2013-03-01 08:03:00 +01:00
Clifford Wolf	a321a5c412	Moved stand-alone libs to libs/ directory and added libs/subcircuit	2013-02-27 09:32:19 +01:00
Clifford Wolf	4f0c2862a0	Added support for verilog genblock[index].member syntax	2013-02-26 13:18:22 +01:00