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Code Activity
3963 commits 98 branches 53 tags 45 MiB
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3963 commits

Author SHA1 Message Date
Udi Finkelstein
73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Udi Finkelstein
80d9d15f1c reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files 2018-06-05 18:00:06 +03:00
Clifford Wolf
4372cf690d Add (* gclk *) attribute support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 13:25:42 +02:00
Clifford Wolf
f273291dfe Add setundef -anyseq / -anyconst support to -undriven mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 11:57:28 +02:00
Clifford Wolf
4cd6d5556a Add "setundef -anyconst" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-06-01 11:49:58 +02:00
Clifford Wolf
3ab79a231b Bugfix in handling of array instances with empty ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-31 18:09:31 +02:00
Clifford Wolf
7f0548c16f Update examples/cmos/counter.ys to use "synth" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 14:17:36 +02:00
Clifford Wolf
7fecc3c199 Make -nordff the default in "prep" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 13:17:09 +02:00
Clifford Wolf
a77e27ab15 Update ABC to git rev 6df1396 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-30 13:10:10 +02:00
Clifford Wolf
cee4b1e6bc Disable memory_dff for initialized FFs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 17:16:15 +02:00
Clifford Wolf
74efafc1cf Add some cleanup code to memory_nordff 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 16:42:06 +02:00
Clifford Wolf
9a946c207f Add comment to VIPER work-around 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-28 13:36:35 +02:00
Clifford Wolf
001c9f1d45 Fix Verific handling of single-bit anyseq/anyconst wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-25 15:41:45 +02:00
Clifford Wolf
251562a491 Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 18:13:38 +02:00
Clifford Wolf
4d645f0fce Fix verific handling of anyconst/anyseq attributes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-24 17:07:06 +02:00
Clifford Wolf
a5f4b44745
Merge pull request from rqou/emscripten-and-abc 
Add option to statically link abc; emscripten fixes
 2018-05-19 08:42:45 +02:00
Robert Ou
bea71e71ca Force abc to align memory to 8 bytes 
Apparently abc has a memory pool implementation that by default returns
memory that is unaligned. There is a workaround in the abc makefile that
uses uname to look for "arm" specifically and then sets the alignment.
However, ARM is not the only platform that requires proper alignment
(e.g. emscripten does too). For now, pessimistically force the alignment
for 8 bytes all the time (somehow 4 wasn't enough for fixing emscripten
despite being approximately a 32-bit platform).
 2018-05-18 22:53:52 -07:00
Robert Ou
0abe7c6c77 Modify emscripten main to mount nodefs and to run arg as a script 2018-05-18 22:53:52 -07:00
Robert Ou
d9ef793430 Force abc to be linked statically and without threads in emscripten 2018-05-18 22:53:47 -07:00
Robert Ou
9763e4d830 Fix infinite loop in abc command under emscripten 2018-05-18 22:42:39 -07:00
Robert Ou
bd87462b47 Fix reading techlibs under emscripten 2018-05-18 22:42:33 -07:00
Robert Ou
93f79299a5 Add options to disable abc's usage of pthreads and readline 2018-05-18 22:42:24 -07:00
Robert Ou
bfce3a7479 Add an option to statically link abc into yosys 
This is currently incomplete because the output filter no longer works.
 2018-05-18 22:35:28 -07:00
Robert Ou
1b210dbfb7 Makefile: Make abc always use stdint.h 2018-05-18 22:26:29 -07:00
Clifford Wolf
177a989e48
Merge pull request from jimparis/yosys-upstream 
Support SystemVerilog `` extension for macros
 2018-05-17 14:10:24 +02:00
Clifford Wolf
c3be94e967
Merge pull request from olofk/ice40_cells_sim_ports 
Avoid mixing module port declaration styles in ice40 cells_sim.v
 2018-05-17 14:03:58 +02:00
Olof Kindgren
faac2c5595 Avoid mixing module port declaration styles in ice40 cells_sim.v 
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
 2018-05-17 13:54:43 +02:00
Jim Paris
4a229e5b95 Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
Jim Paris
872d8d49e9 Skip spaces around macro arguments 2018-05-17 00:06:49 -04:00
Clifford Wolf
a7281930c5 Fix handling of anyconst/anyseq attrs in VHDL code via Verific 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 19:27:00 +02:00
Aman Goel
6e63df6dd0 Correction to -expose with setundef 2018-05-15 13:06:23 -04:00
Clifford Wolf
4b6c0e331d Remove mercurial from build instructions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 14:19:05 +02:00
Clifford Wolf
fe80b39f56 Fix iopadmap for loops between tristate IO buffers 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 14:02:27 +02:00
Clifford Wolf
edd297fb1c Fix iopadmap for cases where IO pins already have buffers on them 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-15 13:13:43 +02:00
Aman Goel
8b9a8c7f91 Minor correction 
Minor typo error correction in -expose with setundef
 2018-05-14 18:58:49 -04:00
Aman Goel
b4a303a1b7 Corrections to option -expose in setundef pass 2018-05-13 20:13:54 -04:00
Aman Goel
9286acb687 Add option -expose to setundef pass 
Option -expose converts undriven wires to inputs.

Example usage: setundef -undriven -expose [selection]
 2018-05-13 16:53:35 -04:00
Clifford Wolf
0fad1570b5 Some cleanups in setundef.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-13 16:36:12 +02:00
Clifford Wolf
ae33026799 Use $(OS) in makefile to check for Darwin 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-13 13:29:18 +02:00
Clifford Wolf
bab39eacce
Merge pull request from thefallenidealist/FreeBSD_build 
FreeBSD build
 2018-05-13 13:27:14 +02:00
Christian Krämer
c1ecb1b2f1 Add "#ifdef __FreeBSD__" 
(Re-commit e3575a8 with corrected author field)
 2018-05-13 13:08:26 +02:00
Clifford Wolf
1167538d26 Revert "Add "#ifdef __FreeBSD__"" 
This reverts commit e3575a86c5.
 2018-05-13 13:06:36 +02:00
Sergiusz Bazanski
7d076f071e Also interpret '&' in liberty functions 2018-05-12 20:55:31 +02:00
Clifford Wolf
587056447e Add optimization of tristate buffer with constant control input 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 15:18:27 +02:00
Clifford Wolf
11406a8082 Add "hierarchy -simcheck" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-12 13:59:13 +02:00
Johnny Sorocil
5b9f73cd91 update README 2018-05-06 18:22:18 +02:00
Johnny Sorocil
0295213bec autotest.sh: Change from /bin/bash to /usr/bin/env bash 
This enables running tests on Unix systems which are not shipped with
bash installed in /bin/bash (eg *BSDs and Solaris).
 2018-05-06 15:26:23 +02:00
Johnny Sorocil
74f2787b10 Enable building on FreeBSD 2018-05-06 15:19:44 +02:00
Clifford Wolf
24e6401617 Further improve handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 14:32:04 +02:00
Clifford Wolf
3e67497ec2 Fix handling of zero-length SVA consecutive repetition 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-05-05 13:58:01 +02:00