89 commits

Author	SHA1	Message	Date
Clifford Wolf	adf1754729	Add $shiftx support to verilog front-end	2017-10-07 13:40:54 +02:00
Clifford Wolf	65f91e5120	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	2017-10-03 17:31:21 +02:00
dh73	e480847753	Fixed wrong declaration in Verilog backend	2017-10-01 11:11:32 -05:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00
Clifford Wolf	05cdd58c8d	Add $_ANDNOT_ and $_ORNOT_ gates	2017-05-17 09:08:29 +02:00
Clifford Wolf	ce132cf652	Cleanups and fixed in write_verilog regarding reg init	2016-11-16 12:00:39 +01:00
Clifford Wolf	3db2ac4e00	Added hex constant support to write_verilog	2016-11-03 12:13:23 +01:00
Clifford Wolf	caa2fc62ef	Adde "write_verilog -renameprefix -v"	2016-11-01 11:30:27 +01:00
Clifford Wolf	75bf7416f0	Bugfix in partial mem write handling in verilog back-end	2016-08-20 13:06:06 +02:00
Clifford Wolf	9b8e06bee1	Added missing support for mem read enable ports to verilog back-end	2016-08-18 21:47:02 +02:00
Clifford Wolf	f0a8713fea	Fixed upto handling in verilog back-end	2016-08-15 08:26:20 +02:00
Clifford Wolf	5fe13a16ea	Added "write_verilog -defparam"	2016-07-30 12:46:06 +02:00
Clifford Wolf	7fa61cba1b	Added "write_verilog -nodec -nostr"	2016-07-30 12:38:40 +02:00
Clifford Wolf	0bc95f1e04	Added "yosys -D" feature	2016-04-21 23:28:37 +02:00
Clifford Wolf	2a8d5e64f5	Bugfix in write_verilog for RTLIL processes	2016-03-14 13:03:28 +01:00
Clifford Wolf	4ac202e2a5	Bugfixes in writing of memories as Verilog	2015-09-25 13:49:26 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Clifford Wolf	0350074819	Re-created command-reference-manual.tex, copied some doc fixes to online help	2015-08-14 11:27:19 +02:00
Clifford Wolf	84bf862f7c	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
luke whittlesey	2f90499e3d	$mem cell in verilog backend : grouped writes by clock	2015-06-08 17:35:40 -04:00
luke whittlesey	a8fe040906	Bug fix in $mem verilog backend + changed tests/bram flow of make test.	2015-06-04 16:12:40 -04:00
Clifford Wolf	4744bb95fb	Some fixes for $mem in verilog back-end	2015-05-20 13:55:50 +02:00
Clifford Wolf	42348cddd9	Merge pull request #63 from wluker/verilog-backend-mem ... Fixed bug in $mem cell verilog code generation.	2015-05-11 21:38:06 +02:00
luke whittlesey	3bb5f064b8	Fixed bug in $mem cell verilog code generation.	2015-05-11 14:05:18 -04:00
Clifford Wolf	9e56739634	Disabled broken $mem support in verilog backend	2015-05-10 21:38:41 +02:00
luke whittlesey	6de8fea2c7	Made changes recommended by Clifford Wolf ... ... Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector.	2015-05-10 11:33:24 -04:00
luke whittlesey	2c1e150297	Verilog backend for $mem cells should now be able to handle different ... write-enable bits and RD_TRANSPARENT parameter settings.	2015-05-08 15:29:51 -04:00
luke whittlesey	c0b68f4848	Added support for $mem cells in the verilog backend.	2015-05-07 13:03:09 -04:00
Clifford Wolf	d176e613c2	Minor fixes in handling of "init" attribute	2015-04-09 15:12:26 +02:00
Clifford Wolf	b0c0ede879	Added "init" attribute support to verilog backend	2015-04-04 18:06:52 +02:00
Clifford Wolf	67e6dcd34a	Added Verilog backend $dffsr support	2015-03-18 08:01:37 +01:00
Clifford Wolf	756b4064b2	Fixed "write_verilog -attr2comment" handling of "*/" in strings	2015-02-13 22:48:10 +01:00
Clifford Wolf	43951099cf	Added dict/pool.sort()	2015-01-24 00:13:27 +01:00
Clifford Wolf	146f769bee	Cosmetic changes in verilog output format	2015-01-02 22:57:08 +01:00
Clifford Wolf	9e6fb0b02c	Replaced std::unordered_map as implementation for Yosys::dict	2014-12-26 21:35:22 +01:00
Clifford Wolf	a6c96b986b	Added Yosys::{dict,nodict,vector} container types	2014-12-26 10:53:21 +01:00
Clifford Wolf	5df192e71c	Added $dffe support to write_verilog	2014-12-20 00:03:20 +01:00
Clifford Wolf	461594bb83	Fixed generation of temp names in verilog backend	2014-11-07 14:40:06 +01:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Clifford Wolf	9329a76818	Various bug fixes (related to $macc model testing)	2014-09-06 20:30:46 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	b9cb483f3e	Using $pos models for $bu0	2014-09-03 21:20:59 +02:00
Clifford Wolf	5dce303a2a	Changed backend-api from FILE to std::ostream	2014-08-23 13:54:21 +02:00
Clifford Wolf	f82c978e08	Fixed AOI/OAI expr handling in verilog backend	2014-08-16 22:05:09 +02:00
Clifford Wolf	47c2637a96	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_	2014-08-16 18:29:39 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	746aac540b	Refactoring of CellType class	2014-08-14 15:46:51 +02:00
Clifford Wolf	88cf00ce78	Be more conservative with printing decimal numbers in verilog backend	2014-08-02 21:54:02 +02:00