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Author	SHA1	Message	Date
Clifford Wolf	494e5f24f9	Added "synth_ice40 -abc2"	2015-12-08 11:16:26 +01:00
Clifford Wolf	4d0a6dac7b	Merge pull request #108 from cseed/master ... Added LO to ICESTORM_LC for LUT cascade route.	2015-12-07 03:32:20 +01:00
Cotton Seed	9f5b6e4cbc	Added LO to ICESTORM_LC for LUT cascade route.	2015-12-06 17:24:48 -05:00
Clifford Wolf	1ea6db3db8	Improved proc_mux performance for huge always blocks	2015-12-02 22:02:20 +01:00
Clifford Wolf	33a5b28e25	Added default values for hashlib at() methods	2015-12-02 20:41:57 +01:00
Clifford Wolf	276101f032	Re-added SigMap::allbits()	2015-11-30 19:43:52 +01:00
Clifford Wolf	0f94902125	Added tests/simple/graphtest.v	2015-11-30 11:41:12 +01:00
Clifford Wolf	4a697accd4	Fixed oom bug in ilang parser	2015-11-29 20:30:32 +01:00
Clifford Wolf	32f5ee117c	Fixed performance bug in ilang parser	2015-11-27 19:46:47 +01:00
Clifford Wolf	a7ffb85690	Merge branch 'master' of github.com:cliffordwolf/yosys	2015-11-26 18:24:23 +01:00
Clifford Wolf	6459e3ac39	Removed dangling ';' in rtlil.h	2015-11-26 18:11:34 +01:00
Clifford Wolf	0793f1b196	Added ice40_ffinit pass	2015-11-26 18:11:06 +01:00
Clifford Wolf	ab2d8e5c8c	Added PRIM_DLATCHRS support to verific front-end	2015-11-24 12:16:19 +01:00
Clifford Wolf	8ff229a3ea	Fixed WE/RE usage in iCE40 BRAM mapping	2015-11-24 10:51:34 +01:00
Clifford Wolf	c86fbae3d1	Fixed handling of re-declarations of wires in tasks and functions	2015-11-23 17:09:57 +01:00
Clifford Wolf	e61c7f887a	Added torder command	2015-11-19 15:34:32 +01:00
Clifford Wolf	415e0a1b90	Fixed performance bug in Verific importer	2015-11-16 12:38:56 +01:00
Clifford Wolf	b18f3a2974	Changes for Verific 3.16_484_32_151112	2015-11-12 19:28:14 +01:00
Clifford Wolf	fd3e10c295	Link to vlsitechnology.org for liberty files	2015-11-12 13:15:19 +01:00
Clifford Wolf	7ae3d1b5a9	More bugfixes in handling of parameters in tasks and functions	2015-11-12 13:02:36 +01:00
Clifford Wolf	34f2b84fb6	Fixed handling of parameters and localparams in functions	2015-11-11 10:54:35 +01:00
Clifford Wolf	d98d99aec6	Added "abc -g"	2015-11-10 11:10:11 +01:00
Clifford Wolf	faa3da5a1b	Merge pull request #97 from zeldin/master ... Fix a segfault in dffinit when the value has too few bits	2015-11-08 22:16:49 +01:00
Marcus Comstedt	8c2bdef36d	Fix a segfault in dffinit when the value has too few bits ... The code was already trying to add the required number of bits, but fell one short of the mark.	2015-11-08 19:16:56 +01:00
Clifford Wolf	1ec6429bad	Added "singleton" pass	2015-11-07 19:10:43 +01:00
Clifford Wolf	3ad742056b	Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling	2015-11-06 17:02:16 +01:00
Clifford Wolf	f401eeb0cf	Bugfix in mapping $tribuf to $_TBUF_	2015-11-05 12:37:43 +01:00
Clifford Wolf	ddf3e2dc65	Bugfix in memory_dff	2015-10-31 22:01:41 +01:00
Clifford Wolf	ccdbf41be6	Improvements in wreduce	2015-10-31 13:39:30 +01:00
Clifford Wolf	864808992b	Bugfix in Xilinx LUT mapping	2015-10-30 13:58:03 +01:00
Clifford Wolf	1e32e4bdae	Improved SigMap performance	2015-10-28 11:21:55 +01:00
Clifford Wolf	e69efec588	Improvements in new SigMap	2015-10-28 00:39:53 +01:00
Clifford Wolf	0c202a2549	Use mfp<> in equiv_mark	2015-10-27 19:15:35 +01:00
Clifford Wolf	f3db70d2f3	Removed old SigMap implementation	2015-10-27 15:09:44 +01:00
Clifford Wolf	09b4050f2e	Added hashlib::mfp and new SigMap	2015-10-27 15:04:47 +01:00
Clifford Wolf	27714acd8a	Improvements in equiv_struct	2015-10-25 22:04:20 +01:00
Clifford Wolf	d014ba2d0e	Major refactoring of equiv_struct	2015-10-25 19:31:29 +01:00
Clifford Wolf	207736b4ee	Import more std:: stuff into Yosys namespace	2015-10-25 19:30:49 +01:00
Clifford Wolf	da923c198e	Added "equiv_add -cell"	2015-10-25 14:35:40 +01:00
Clifford Wolf	83bd27bf6e	equiv_struct now creates equiv_merged attributes	2015-10-25 02:15:20 +02:00
Clifford Wolf	453736d918	Improvements in equiv_struct	2015-10-24 23:04:17 +02:00
Clifford Wolf	7f110e7018	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	2015-10-24 22:56:40 +02:00
Clifford Wolf	6af8076967	improvement in "stat"	2015-10-24 21:56:53 +02:00
Clifford Wolf	a1c3df7fe4	Fixed driver conflict handling (various cmds)	2015-10-24 19:23:30 +02:00
Clifford Wolf	6fe48cf41e	equiv_purge bugfix, using SigChunk in Yosys namespace	2015-10-24 19:09:45 +02:00
Clifford Wolf	2a0f577f83	Fixed handling of driver-driver conflicts in wreduce	2015-10-24 13:44:35 +02:00
Clifford Wolf	4cec1c058d	Added equiv_mark command	2015-10-23 23:56:58 +02:00
Clifford Wolf	c35db8c19e	Disabled "Skipping blackbox module" msg in show command	2015-10-23 20:11:05 +02:00
Clifford Wolf	281a033e92	Added support for ":" as comment symbol after ;-parsing	2015-10-23 20:08:33 +02:00
Clifford Wolf	15a67392f1	Also merge $equiv cells in equiv_struct	2015-10-23 15:26:58 +02:00