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4012 commits 99 branches 53 tags 46 MiB
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Author SHA1 Message Date
Clifford Wolf
3bb9288d65 Improve Verific importer blackbox handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
8e13f2913d Add "write_edif -attrprop" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
05e1c39064 Fix compiler warning in verific.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Tim Ansell
3661c27acd Fix misspelling in issue_template.md 
It's been bugging me :-P
 2018-10-08 11:38:10 -07:00
Adrian Wheeldon
81d77c4911 Fix IdString M in setup_stdcells() 2018-10-08 11:38:10 -07:00
Clifford Wolf
ea82191c57 Add inout ports to cells_xtra.v 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Tim Ansell
cd261795ba xilinx: Adding missing inout IO port to IOBUF 2018-10-08 11:38:10 -07:00
Tom Verbeure
b8950bd603 Fix for issue 594. 2018-10-08 11:38:10 -07:00
Dan Gisselquist
d3be61b9dc Add read_verilog $changed support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
David Shah
ae8637cd63 ecp5: Don't map ROMs to DRAM 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
7d88d851d8 Fix handling of $past 2nd argument in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
b3de38d357 Update to v2 YosysVS template 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
89ef6600bc Add "read_verilog -noassert -noassume -assert-assumes" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
e8431d1508 Added support for ommited "parameter" in Verilog-2001 style parameter decl in SV mode 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
a9085ff4af Update CHANGELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Miodrag Milanovic
6cf9fca93b added prefix to FDirection constants, fixing windows build 2018-10-08 11:38:10 -07:00
Clifford Wolf
f73e7116f9 Update CHANGLELOG 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Clifford Wolf
8340d44986 Update Changelog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-08 11:38:10 -07:00
Miodrag Milanovic
24951ddc77 Fix Cygwin build and document needed packages 2018-10-08 11:38:10 -07:00
acw1251
33ac82a5fe Fixed typo in "verilog_write" help message 2018-10-08 11:38:10 -07:00
Jim Lawson
6a809a1bb1 Merge remote-tracking branch 'upstream/master' 2018-09-17 14:31:57 -07:00
Clifford Wolf
592a82c0ad
Merge pull request #625 from aman-goel/master 
Minor revision to -expose in setundef pass
 2018-09-14 12:36:13 +02:00
Clifford Wolf
1936d4408e
Merge pull request #627 from acw1251/master 
Fixed minor typo in "sim" help message
 2018-09-14 12:34:51 +02:00
acw1251
5fe16c25b8 Fixed minor typo in "sim" help message 2018-09-12 18:34:27 -04:00
Aman Goel
75c1f8d241 Minor revision to -expose in setundef pass 
Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
 2018-09-10 21:44:36 -04:00
Clifford Wolf
51f1bbeeb0 Add iCE40 SB_SPRAM256KA simulation model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-10 11:57:24 +02:00
Clifford Wolf
12440fcc8f Add $lut support to Verilog back-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-06 00:18:01 +02:00
Clifford Wolf
5d9d22f66d Add "verific -L <int>" option 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-04 20:06:10 +02:00
Clifford Wolf
0b7a18470b Add "make ystests" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-30 12:26:26 +02:00
Miodrag Milanović
d36d11936f Add GCC to osx deps (#620) 
* Add GCC to osx deps

* Force gcc-7 install
 2018-08-28 17:17:33 +02:00
Jim Lawson
036e3f9c1b
Merge pull request #4 from YosysHQ/master 
merge with YosysHQ master
 2018-08-28 08:03:40 -07:00
Clifford Wolf
cf2ea21899
Merge pull request #619 from mmicko/master 
Remove mercurial, since it is not needed anymore
 2018-08-28 13:37:11 +02:00
Miodrag Milanovic
92896a58be Remove mercurial, since it is not needed anymore 2018-08-28 13:11:41 +02:00
Clifford Wolf
373244c5ab
Merge pull request #618 from ucb-bar/firrtl+modules+shiftfixes 
Add support for modules.
 2018-08-28 12:04:49 +02:00
Jim Lawson
e217c6c52f Merge branch 'master' into firrtl+modules+shiftfixes 2018-08-27 12:13:04 -07:00
Jim Lawson
380c6f0e97 Remove unused functions. 2018-08-27 10:18:33 -07:00
Jim Lawson
604b5d4e20
Merge pull request #3 from YosysHQ/master 
merge with YosysHQ
 2018-08-27 10:09:39 -07:00
Clifford Wolf
ddc1761f1a Add "make coverage" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-27 14:22:21 +02:00
Clifford Wolf
9e845bd254 Add ENABLE_GCOV build option 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-27 13:27:05 +02:00
Clifford Wolf
96d79878b9
Merge pull request #617 from mmicko/master 
static link flag on main executable
 2018-08-25 16:40:55 +02:00
Miodrag Milanovic
306a010e19 static link flag on main executable 2018-08-25 16:20:44 +02:00
Jim Lawson
93d19dc2fb Add support for module instances. 
Don't pad logical operands to one bit.
Use operand width and signedness in $reduce_bool.
Shift amounts are unsigned and shouldn't be padded.
Group "is invalid" with the wire declaration, not its use (otherwise it is incorrectly wired to 0).
 2018-08-23 14:35:11 -07:00
Clifford Wolf
4d269f9b25
Merge pull request #610 from udif/udif_specify_round2 
More specify/endspecify fixes
 2018-08-23 14:43:25 +02:00
Clifford Wolf
92c2a04e19
Merge pull request #614 from udif/pr_disable_dump_ptr 
Added -no_dump_ptr flag for AST dump options in 'read_verilog'
 2018-08-23 14:41:41 +02:00
Udi Finkelstein
042b3074f8 Added -no_dump_ptr flag for AST dump options in 'read_verilog' 
This option disables the memory pointer display.
This is useful when diff'ing different dumps because otherwise the node pointers
makes every diff line different when the AST content is the same.
 2018-08-23 15:26:02 +03:00
Jim Lawson
2c0601eb6f
Merge pull request #1 from YosysHQ/master 
merge with YosysHQ master
 2018-08-22 08:42:34 -07:00
Clifford Wolf
408077769f Add "verific -work" help message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-22 17:22:24 +02:00
Clifford Wolf
4b02ee9162 Add Verific -work parameter 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-08-22 13:30:22 +02:00
Udi Finkelstein
fbfc677df3 Fixed all known specify/endspecify issues, without breaking 'make test'. 
Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts,
due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
 2018-08-20 17:27:45 +03:00
Udi Finkelstein
95241c8f4d Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , 
(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.
 2018-08-20 00:08:08 +03:00