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Author SHA1 Message Date
Dag Lem
39fea32c6e Add support for packed multidimensional arrays 
* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
 2024-02-11 11:26:52 -05:00
Jannis Harder
ac0fb2e301
Merge pull request #4199 from tpwrules/test-fix 
tests/various/clk2fflogic_effects.sh: fix on macOS
 2024-02-11 02:32:42 +01:00
github-actions[bot]
0b835f28ca Bump version 2024-02-11 00:17:25 +00:00
Martin Povišer
c46ebf28c2
Merge pull request #4198 from passingglance/patch-1 
Update CHAPTER_Basics.rst
 2024-02-10 23:16:30 +01:00
Thomas Watson
10e06f9b66 tests/various/clk2fflogic_effects.sh: remove /tmp use 
Might not be accessible.
 2024-02-10 15:09:54 -06:00
Thomas Watson
b1f8308772 tests/various/clk2fflogic_effects.sh: fix tail invocation 
Previous syntax is a GNU extension and not accepted by macOS. Use
documented -n option instead, compatible with POSIX-compliant tail
implementations.
 2024-02-10 15:07:55 -06:00
passingglance
2b89a5cced
Update CHAPTER_Basics.rst 
Fix typo in Fig. 2.2 caption.
 2024-02-10 10:52:20 -08:00
github-actions[bot]
31dbd915ca Bump version 2024-02-10 00:15:13 +00:00
Miodrag Milanovic
46838172c2 Next dev cycle 2024-02-09 08:19:14 +01:00
Miodrag Milanovic
543faed9c8 Release version 0.38 2024-02-09 08:16:24 +01:00
github-actions[bot]
8e3a718e30 Bump version 2024-02-09 00:15:19 +00:00
Miodrag Milanović
2f4c917dac
Merge pull request #4181 from povik/ci-cxxstd-fix 
ci: Fix CXXSTD typo
 2024-02-08 18:55:47 +01:00
Miodrag Milanović
d808258583
Merge pull request #4193 from povik/opt_lut-help 
opt_lut: Remove leftover `-dlogic` help
 2024-02-08 18:54:16 +01:00
Martin Povišer
043f1e2bcb opt_lut: Remove leftover -dlogic help 2024-02-08 17:49:44 +01:00
Martin Povišer
af1a5cfeb9 Address SigBit/SigSpec confusion issues under c++20 2024-02-08 17:48:36 +01:00
Martin Povišer
66479a2232 hashlib: Add missing stdint.h include 
We use `uint32_t` `uint64_t` etc. so add an explicit include.
 2024-02-08 14:27:12 +00:00
Catherine
1236bb65b6 read_verilog: don't include empty opt_sva_label in span. 
Consider this SystemVerilog file:

    module top(...);
      input clk;
      input [7:0] data;
      input ack;

      always @(posedge clk)
        if (ack) begin
          assert(data != 8'h0a);
        end
    endmodule

Before this commit, the span for the assert was:

        if (ack) begin>
          assert(data != 8'h0a)<;

After this commit, the span for the assert is:

        if (ack) begin
          >assert(data != 8'h0a)<;

This helps editor integrations that only look at the beginning
of the span.
 2024-02-08 14:25:35 +00:00
Miodrag Milanović
675b8a7319
Merge pull request #4190 from YosysHQ/xdg 
Follow the XDG Base Directory Specification
 2024-02-08 14:05:31 +01:00
Miodrag Milanovic
a38273c19d add log_suppressed and fixed formatting 2024-02-08 12:19:42 +01:00
Martin Povišer
a1824ba5b6
Merge pull request #4187 from povik/synth-help 
synth: Run script in full in help mode
 2024-02-08 09:56:48 +01:00
Miodrag Milanovic
2797d67569 Move block and change message to debug 2024-02-08 09:19:19 +01:00
Miodrag Milanovic
f785eef685 Merge branch 'master' of github.com:hakan-demirli/yosys into xdg 2024-02-08 09:03:52 +01:00
Martin Povišer
7a3316dd78 synth: Tweak phrasing of -booth help 2024-02-08 00:05:15 +01:00
Martin Povišer
a98d363d9d synth: Run script in full in help mode 2024-02-08 00:05:15 +01:00
github-actions[bot]
16ff3e0a30 Bump version 2024-02-07 00:14:46 +00:00
Miodrag Milanović
269c50f90e
Merge pull request #4130 from jix/hierarchy-defer-notop 
hierarchy: Without a known top module, derive all deferred modules
 2024-02-06 12:08:01 +01:00
Miodrag Milanovic
d00843d436 Add -nordff to test 2024-02-06 10:36:30 +01:00
Jannis Harder
0470cbb00d hierarchy: Without a known top module, derive all deferred modules 
This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
 2024-02-06 10:31:40 +01:00
Miodrag Milanović
5d3e4c5c7a
Merge pull request #4182 from QuantamHD/fix_aldff 
verific: Improves aldff inference in verific importer
 2024-02-06 08:19:43 +01:00
github-actions[bot]
1df2a209e5 Bump version 2024-02-06 00:15:26 +00:00
Claire Xen
1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite 
Add API to overwrite existing pass from plugin
 2024-02-05 23:49:24 +01:00
Martin Povišer
57db87c99f py_wrap_generator: Handle const-qualified callbacks 2024-02-05 17:25:55 +01:00
N. Engelhardt
2422dd6845
Merge pull request #4153 from Coloquinte/blif_delay_constraints 
Issue a warning instead of a syntax error for blif delay constraints
 2024-02-05 15:14:05 +01:00
N. Engelhardt
f96e27ac14
Merge pull request #4123 from povik/clean-opt_clean 
opt_clean: Add commentary, remove dead code
 2024-02-05 15:08:34 +01:00
Ethan Mahintorabi
ff578ecabd
fix formatting 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:23:04 +00:00
Ethan Mahintorabi
bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer 
The following SV module at HEAD imported with verific,

```systemverilog
    module my_module(
      input logic [4:0] a,
      input logic clk,
      input logic enable,
      output logic [4:0] z
    );

    reg [4:0] pipeline_register;
    always @(posedge clk) begin
      pipeline_register <= enable ? a : pipeline_register;
    end
    assign z = pipeline_register;

    endmodule : my_module

```

results in the following output verilog

```systemverilog
/* Generated by 0.36 */

(* top =  1  *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
  wire [4:0] _0_;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
  input [4:0] a;
  wire [4:0] a;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
  input clk;
  wire clk;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
  input enable;
  wire enable;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
  output [4:0] z;
  wire [4:0] z;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
  \$aldff  #(
    .ALOAD_POLARITY(32'd1),
    .CLK_POLARITY(32'd1),
    .WIDTH(32'd5)
  ) _1_ (
    .AD(5'hxx),
    .ALOAD(1'h0),
    .CLK(clk),
    .D(_0_),
    .Q(z)
  );
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
  \$mux  #(
    .WIDTH(32'd5)
  ) _2_ (
    .A(z),
    .B(a),
    .S(enable),
    .Y(_0_)
  );
endmodule
```

Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.

My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:10:25 +00:00
Krystine Sherwin
0cdd4273b4
ci: ignore yosys-config return code 2024-02-05 15:41:50 +13:00
Martin Povišer
97b8ee5ab9 ci: Get a dump of yosys-config into the build log 2024-02-04 23:29:46 +01:00
Martin Povišer
3f457f2388 ci: Fix CXXSTD typo 2024-02-04 23:21:06 +01:00
github-actions[bot]
f5420d720c Bump version 2024-02-04 00:17:08 +00:00
Catherine
3caac53827
Merge pull request #4128 from whitequark/check-cell 
Add `$check` cell to represent assertions with messages
 2024-02-03 18:39:00 +00:00
Jannis Harder
ffb82df33c Additional tests for FV $check compatibility 2024-02-02 16:07:10 +01:00
hakan-demirli
7dbe288d6f fix: descriptive logs 2024-02-02 02:39:04 +03:00
hakan-demirli
c1d3288654 chore: use similar variable/function names 2024-02-02 01:25:58 +03:00
Catherine
c7bf0e3b8f Add new $check cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
Jannis Harder
e1a59ba80b async2sync, clk2fflogic: Add support for $check and $print cells 2024-02-01 20:10:39 +01:00
Jannis Harder
6c4902313b chformal: Support $check cells and add chformal -lower 
This adds support for `$check` cells in chformal and adds a `-lower`
mode which converts `$check` cells into `$assert` etc. cells with a
`$print` cell to output the `$check` message.
 2024-02-01 20:10:39 +01:00
Jannis Harder
331ac5285f tests: Run async2sync before sat and/or sim to handle $check cells 
Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.

While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.
 2024-02-01 16:14:11 +01:00
Jannis Harder
2baa578d94 Remove too fragile smtlib2_module test 
This compares the write_smt2 output pretty much verbatim, which contains
auto generated private names and fixes an arbitrary ordering. The tested
functionality is also covered by SBY tests which actually interpret the
write_smt2 output using an SMT solver and thus are much more robust, so
we can safely remove this test.
 2024-02-01 16:14:11 +01:00
N. Engelhardt
9f27923782
Merge pull request #4173 from YosysHQ/verific_complex 
verific: add option to skip simplifying complex ports
 2024-02-01 12:08:40 +01:00