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Author SHA1 Message Date
Emil J. Tywoniak
3f59eb038c WIP opt_clean: garbage collect against the signorm index
BROKEN: 12 tests fail (list below). Committed to keep the work resumable,
not because it is ready.

opt_clean stops calling sigNormalize(false) and, for modules carrying an
index, runs a tracing GC against it instead of rebuilding its own view of
the netlist: mark from keep/output/$input_port roots through
wire->driverCell_ (one dereference per input bit, no wire2driver
hashtable, no assign_map), sweep cells, sweep wires on fanout emptiness,
then compact the sigmap over the survivors before the wires are freed.
Per the design decision, it does not rename or rewire: where the old pass
collapsed a public wire and its driver's wire into one, this keeps both
plus the alias in the sigmap, which is fine to traverse.

Kernel support: SigNormIndex::compact() (mfp cannot erase, so the sigmap
only ever grows -- opt_clean is the only pass that knows what is garbage,
hence the only one that can shrink it), an index-aware
Module::remove(pool<Wire*>), and signorm_sigmap() normalizing fully
rather than only flushing, since a caller reading the *index* rather than
just the map has to see it settled.

What this is worth on its own: 4.75s -> 4.54s on a 2000-stage pipeline
(Debug), against main-dbg's 4.56s. The real win needs opt_dff to stop
tearing the index down too -- together they are 3.39s -- but opt_dff
regresses optimization quality under signorm and is left denormalizing.
Neither change pays off without the other, which is the point of keeping
this around. See g/signorm-opt_clean-analysis.md.

Failing: arch/fabulous/fsm, arch/gatemate/fsm,
arch/quicklogic/qlf_k6n10f/t_mem{1,5,6},
asicworld/code_verilog_tutorial_explicit, memories/wide_all, sat/share,
various/{bug3515,bug4909,muxcover,port_sign_extend}.

port_sign_extend is diagnosed and is not this pass's fault: Design::add()
indexes a module while it is still empty, so setup_module_inputs() finds
no ports and the index stays incomplete for wires added afterwards. Same
defect as submod. muxcover is another marker-cell count. sat/share is the
one still worth suspecting the GC over.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo
2026-07-21 15:10:36 +02:00
Emil J. Tywoniak
a7938567fe rtlil: sort twines by string, not by ID, in sort methods 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
9552cba923 rtlil: options for dumping twines 2026-07-20 15:01:30 +02:00
Emil J. Tywoniak
92b16718c9 twine: fix replayability, reduce TwineSearch usage 2026-07-20 13:57:10 +02:00
Emil J. Tywoniak
fb4f567456 twine: auto type WIP 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
93ea3dfd4b rtlil: fix twine handling 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
c08fb7f3ed WIP migration to twine 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
65f35a88eb WIP migration to twine 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
0f884b6cba twine: avoid TwinePool::lookup 2026-07-20 12:27:18 +02:00
Emil J. Tywoniak
a9a190f70f twine: GC again WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
c8e42bc15b twine: fix another off-by-one 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
94f347a71c twine: fix off-by-one static twine error 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
a5248849d9 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
b01a3694f0 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
77ad54139e WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
e952044215 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
7422b71802 WIP 2026-07-20 12:27:17 +02:00
Emil J. Tywoniak
1210d8e117 WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
30bc1c23ee WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
10436f31cd WIP 2026-07-20 12:27:02 +02:00
Emil J. Tywoniak
f508244f36 rtlil: fix masquerade 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
edb43b93d7 rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge) 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
3da81b2e9d rtlil: Module::clone attaches to source design; callers use clone(dst) 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
be4d67d1a3 rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
84c6c61736 rtlil: extend per-Design meta vector to hold name slot 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
d7f88dd3a0 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
0bff07d55c rtlil: add Module* back-pointer to RTLIL::Memory 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
d37581d9d7 rtlil: add per-Design src meta vector + freelist 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
452964e75a rtlil: add Module* back-pointer to inner-process AttrObjects 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
f017bb8a93 twine 2026-07-20 12:26:39 +02:00
Emil J. Tywoniak
fd67ce2b80 WIP 2026-07-17 23:48:54 +02:00
Emil J. Tywoniak
07d5115135 patch: source transfer 2026-07-17 23:48:06 +02:00
Emil J. Tywoniak
e331300c58 patch: fix patch mixins 2026-07-17 23:48:00 +02:00
Emil J. Tywoniak
277b6f47dc rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch 2026-07-17 23:48:00 +02:00
Emil J. Tywoniak
20b0a9934b rtlil: allow friends to use Cell constructors with a factory token pattern 2026-07-17 23:47:08 +02:00
Emil J. Tywoniak
360527af1a rtlil: fix cloneInto in signorm 2026-07-17 23:33:03 +02:00
Emil J. Tywoniak
2fc93aa711 rtlil: sigNormalize Module when added to Design in signorm mode 2026-07-17 23:33:03 +02:00
Jannis Harder
b84beb598f WIP half broken snapshot 2026-07-17 23:32:20 +02:00
Michael Baier
5cd9efefe3 Adding widht checks to backend 2026-07-09 14:34:56 +02:00
nella
c99a037c33
Merge pull request #5886 from YosysHQ/nella/fix-signedness-5745
Fix  `chparam` values are unsigned when using read_verilog frontend
2026-06-18 16:50:22 +00:00
Miodrag Milanovic
8bbc3c359c Remove id2cstr uses in our code base 2026-05-16 19:49:45 +02:00
nella
7d3e56523b Preserve param signedness across overrides. 2026-05-13 16:25:15 +02:00
Codexplorer
e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Emil J. Tywoniak
25b9b796c4 rtlil: complicate extract again for packing 2026-04-24 11:04:19 +02:00
Emil J. Tywoniak
14b0efeced rtlil: simplify extract for performance 2026-04-23 13:58:20 +02:00
Emil J. Tywoniak
ea11453cef rtlil: faster remove2 2026-03-18 23:33:35 +01:00
Robert O'Callahan
b42bb05b63 Parallelize Design::check() 2026-03-06 02:03:21 +00:00
Robert O'Callahan
e2166c4684 Parallelize collect_garbage() 2026-03-06 02:03:21 +00:00
nella
04822c6660 Readd builtin_ff_cell_types for plugin parity. 2026-03-04 12:39:45 +01:00
nella
66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00