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6791 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Eddie Hung
36e38ed46a
Merge pull request #1321 from YosysHQ/eddie/xilinx_srl 
xilinx_srl pass for shift register extraction
 2019-08-30 10:32:03 -07:00
Eddie Hung
9c4e1c6a8f
Format -pwires 2019-08-30 10:27:07 -07:00
Eddie Hung
6e475484b2 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-30 09:37:32 -07:00
David Shah
a94a8f3e40
Merge pull request #1343 from whitequark/diamond-ffs 
Add/update every Diamond FF primitive
 2019-08-30 13:28:21 +01:00
David Shah
91b46ed816 ecp5: Add simulation equivalence check for Diamond FF implementations 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-30 13:27:36 +01:00
whitequark
d9c621f9d1 ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. 2019-08-30 10:05:09 +00:00
whitequark
1e6b60d563 ecp5: allow (and enable by default) GSR on FD/IFS/OFS primitives. 2019-08-30 09:56:19 +00:00
whitequark
6fa8ce93e6 ecp5: add missing FD primitives. 2019-08-30 09:54:48 +00:00
whitequark
7e2825a2a4 ecp5: fix CEMUX on IFS/OFS primitives. 2019-08-30 09:42:33 +00:00
Eddie Hung
694e30a354
Merge pull request #1337 from YosysHQ/eddie/fix_carry_wrapper 
Fix $__ICE40_CARRY_WRAPPER, restore abc9 functionality
 2019-08-29 22:10:45 -07:00
Eddie Hung
1467761060 Fix typo that's gone unnoticed for 5 months!?! 2019-08-29 10:33:28 -07:00
Eddie Hung
25b1670a84 Rename boxes too 2019-08-29 07:03:32 -07:00
Clifford Wolf
89695fd3ab Bump YOSYS_VER 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-29 12:05:26 +02:00
Eddie Hung
13ecd8b0df Add run-test.sh too 2019-08-28 18:47:48 -07:00
Eddie Hung
a4f641f230 Do not overwrite LUT param 2019-08-28 18:46:53 -07:00
Eddie Hung
e301a3dadb Add SB_CARRY to ice40_opt test 2019-08-28 18:46:53 -07:00
Eddie Hung
dd42aa87b9 Add ice40_opt test 2019-08-28 18:46:53 -07:00
Eddie Hung
4eb5847dbd Cleanup 2019-08-28 18:10:33 -07:00
Eddie Hung
d46d38e4d5 Trailing comma 2019-08-28 17:25:54 -07:00
Eddie Hung
f5b4bc847c Adapt to $__ICE40_CARRY_WRAPPER 2019-08-28 17:25:05 -07:00
Eddie Hung
e569f13870 Revert "Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with" 
This reverts commit 2aedee1f0e.
 2019-08-28 17:22:44 -07:00
Eddie Hung
2aedee1f0e Remove $__ICE40_FULL_ADDER handling from ice40_opt; cannot reason with 
CARRY_WRAPPER in the same way since I0 and I3 could be used
 2019-08-28 17:07:36 -07:00
Eddie Hung
077e9d4ada Update box size and timings 2019-08-28 17:07:24 -07:00
Eddie Hung
129df7184a Update to new $__ICE40_CARRY_WRAPPER 2019-08-28 17:07:07 -07:00
Eddie Hung
0af64df10c Account for D port being a constant 2019-08-28 15:32:38 -07:00
Eddie Hung
fc727fa5c9
Merge pull request #1334 from YosysHQ/clifford/async2synclatch 
Add $dlatch support to async2sync
 2019-08-28 12:36:06 -07:00
Eddie Hung
52c4655de3 No need to replace Q of slice since $shiftx is autoremove-d 2019-08-28 11:06:11 -07:00
Eddie Hung
9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
Eddie Hung
11e3eb1009 More cleanup 2019-08-28 10:19:35 -07:00
Eddie Hung
86b538bd02 More cleanup 2019-08-28 10:11:09 -07:00
Eddie Hung
c4d1bd988b Do not use default_params dict, hardcode default values, cleanup 2019-08-28 10:06:40 -07:00
Eddie Hung
64ea147236 Add .gitignore 2019-08-28 09:55:34 -07:00
Eddie Hung
2f493fb465 Use test_pmgen for xilinx_srl 2019-08-28 09:55:09 -07:00
Eddie Hung
c3e9627afe Always generate if no match 2019-08-28 09:54:56 -07:00
Eddie Hung
0ebe2c9831 Rename test_pmgen arg xilinx_srl.{fixed,variable} 2019-08-28 09:27:03 -07:00
Eddie Hung
2e9e745efa Do not simplemap for variable test 2019-08-28 09:26:08 -07:00
Eddie Hung
975aaf190f Add xilinx_srl test 2019-08-28 09:24:19 -07:00
Eddie Hung
ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
David Shah
13424352cc
Merge pull request #1332 from YosysHQ/dave/ecp5gsr 
ecp5: Add GSR and SGSR support
 2019-08-28 12:44:02 +01:00
Clifford Wolf
c84fef92df
Merge pull request #1335 from YosysHQ/clifford/paramap 
Add "paramap" pass
 2019-08-28 10:35:47 +02:00
Clifford Wolf
47ffbf554e Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c Add "paramap" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:03:27 +02:00
Clifford Wolf
c499dc3e73 Add $dlatch support to async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 09:45:22 +02:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init 
In sat: 'x' in init attr should be ignored
 2019-08-28 00:18:14 +02:00
Marcin Kościelnicki
d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
Eddie Hung
eab3c1432b
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap 
Add clock buffer insertion pass, improve iopadmap.
 2019-08-27 10:19:27 -07:00
Eddie Hung
28133432be Ignore all 1'bx in (* init *) 2019-08-27 09:24:59 -07:00
Eddie Hung
00387f3927 Revert to using clean 2019-08-27 09:24:32 -07:00
Marcin Kościelnicki
5fb4b12cb5 improve clkbuf_inhibit propagation upwards through hierarchy 2019-08-27 17:26:47 +02:00
David Shah
fc001b4731 ecp5: Add GSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:07:06 +01:00