Akash Levy
e7e15b6120
fix: add Alpine/musl shims for libtcl and libnsl
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Verific tclmain links -ltcl and -lnsl. Alpine tcl-dev provides
libtcl8.6.so (no libtcl.so symlink), and musl has no libnsl.
Create symlink and stub shared lib to satisfy the linker.
Made-with: Cursor
2026-02-28 12:20:32 -08:00
Akash Levy
0b0c19b271
fix: use SSH_PRIVATE_KEY secret for private submodule access
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Use the same SSH key approach as source-vendor.yml for cloning
private submodules (abc, verific).
Made-with: Cursor
2026-02-28 12:09:28 -08:00
Akash Levy
708637f65a
fix: use PAT for private submodule access (abc, verific)
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Deploy keys are repo-scoped and can't access multiple private repos.
Use a PAT (SUBMODULE_PAT) that has access to all required repos.
Made-with: Cursor
2026-02-28 12:07:03 -08:00
Akash Levy
44beeb5213
fix: use SSH deploy key for private verific submodule checkout
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Made-with: Cursor
2026-02-28 12:05:26 -08:00
Akash Levy
2c1d160930
fix: trigger release workflow on main branch, not master
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Made-with: Cursor
2026-02-28 12:03:52 -08:00
AdvaySingh1
877e97de06
Changed to for chacterization
2026-02-27 15:23:50 -08:00
Akash Levy
fc4ff6ecd2
Add release workflow
2026-02-27 15:01:06 -08:00
Akash Levy
18c3a0b907
Remove old linefile loops stuff
2026-02-27 14:53:44 -08:00
Advay Singh
8974f3473f
Update passes/silimate/infer_ce.cc
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Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
2026-02-27 12:37:49 -08:00
AdvaySingh1
90aa1cc016
Checked out main passes/techmap/clockgate.cc for source attributes and removed logging
2026-02-27 12:24:31 -08:00
AdvaySingh1
ce95d7cbcf
Removed notes.txt
2026-02-27 12:22:29 -08:00
Stan Lee
8ee71ddc7f
bugfix
2026-02-27 12:19:14 -08:00
Stan Lee
93af5a5232
in order
2026-02-27 12:17:43 -08:00
Stan Lee
c42d2c2d03
support for nested structs
2026-02-27 11:54:43 -08:00
Stan Lee
d36e2f7d17
resolve accidental change
2026-02-27 11:40:13 -08:00
Stan Lee
03ce300b49
another indent
2026-02-27 11:29:31 -08:00
Stan Lee
fa1267e0cb
fix indents
2026-02-27 11:27:37 -08:00
Stan Lee
ae3b9b74e2
ready
2026-02-27 11:25:10 -08:00
Stan Lee
48894488f1
better method for assigning fsthandles
2026-02-27 11:25:10 -08:00
Stan Lee
0aaca679ce
better but not ideal
2026-02-27 11:25:10 -08:00
Stan Lee
5bdc2d3451
working implementation that i will improvee further
2026-02-27 11:25:10 -08:00
AdvaySingh1
3cee420bf9
Merge branch 'main' into sat_clkgate
2026-02-27 11:15:22 -08:00
likeamahoney
e9442194f2
support automatic lifetime qualifier on procedural variables
2026-02-27 20:42:52 +03:00
tondapusili
f46b8d2a44
silimate: add opt_timing_balance pass and tests
2026-02-27 09:13:39 -08:00
Miodrag Milanović
687a36af38
Merge pull request #5711 from YosysHQ/gowin_warning
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gowin: remove spurious warning
2026-02-27 14:04:27 +01:00
Miodrag Milanovic
7f1f247c56
gowin: remove spurious warning
2026-02-27 13:12:32 +01:00
Miodrag Milanović
2dd71c3ba2
Merge pull request #5709 from YosysHQ/update_abc
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Update ABC as per 2026-02-27
2026-02-27 08:32:34 +01:00
Miodrag Milanovic
b3caec1a93
Update ABC as per 2026-02-27
2026-02-27 07:55:34 +01:00
Andrew Pullin
5970be33fb
abc9: preserve topological-loop asserts with targeted SCC fallback
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A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.
Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).
To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.
Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
2026-02-26 22:30:32 -08:00
Akash Levy
0c663bef4a
Merge pull request #110 from Silimate/negopt_log_flush
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Added log flushes after each negopt pass for clearer logging
2026-02-26 16:09:34 -08:00
Stan Lee
29a1c69f74
move log flush to better spot
2026-02-26 16:01:37 -08:00
Stan Lee
b11eef4fe1
fix bug
2026-02-26 16:00:27 -08:00
tondapusili
2f276d0723
Added log flushes after each negopt pass for clearer logging
2026-02-25 12:15:46 -08:00
nella
2c52546e2a
Fix docs.
2026-02-25 16:42:05 +01:00
Emil J
5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors
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equiv_induct: error on missing model
2026-02-25 15:39:31 +01:00
Miodrag Milanović
fd1ac58767
Merge pull request #5706 from YosysHQ/remove-flake-lock
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Remove already disabled CI job
2026-02-25 11:15:33 +01:00
Miodrag Milanovic
31f7d0d92d
Remove already disabled CI job
2026-02-25 10:36:46 +01:00
Miodrag Milanović
53d8eb43ff
Merge pull request #5702 from YosysHQ/verific_build_all
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Check verific configurations
2026-02-23 09:41:59 +01:00
Miodrag Milanovic
b51110a50b
Build various Verific configurations
2026-02-23 09:01:55 +01:00
Krystine Sherwin
fd311c5501
tests/arch/gowin: Add wr_en test
2026-02-22 09:00:37 +01:00
Krystine Sherwin
2386923b8f
gowin: Fix bram ADA byte enables
2026-02-22 09:00:37 +01:00
Akash Levy
0b46d8b201
Merge pull request #109 from Silimate/clkgate_attr
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Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 17:02:02 -08:00
Akash Levy
c47dd20140
Merge pull request #108 from Silimate/icg_builtin_sim
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Added built in cell alongside sim support for cell
2026-02-20 17:01:20 -08:00
AdvaySingh1
ec537b189f
Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 11:34:50 -08:00
AdvaySingh1
8f5b8cb46c
Added is_clock_gated attr to flops created via clockgate.cc pass
2026-02-20 11:34:08 -08:00
Miodrag Milanović
fb653c4181
Merge pull request #5700 from YosysHQ/wasi_speedup
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CI: WASI - Applying YoWASP changes to script
2026-02-20 18:00:24 +01:00
Miodrag Milanovic
68e47ebcfe
CI: WASI - Applying YoWASP changes to script
2026-02-20 15:23:45 +01:00
Miodrag Milanović
0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify
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abc9: verify post-mapping equivalence by default
2026-02-20 13:41:11 +01:00
Krystine Sherwin
094481739f
memory_libmap: Add -force-params
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Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
2026-02-20 10:57:00 +00:00
Emil J
13795203a1
Merge pull request #5680 from YosysHQ/emi/aiger-add-bounds-checks
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aigerparse: add some bounds checks
2026-02-20 11:53:49 +01:00
