Lofty
d5ea7f7016
Create synth_analogdevices
2026-03-05 05:37:12 +00:00
Lofty
4caffa7ebd
Merge pull request #5725 from yrabbit/disable-wm-2
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GOWIN. Disable read-before-write mode.
2026-03-05 05:36:28 +00:00
Andrew Pullin
6ac8c8cb05
ast: Add support for array-to-array assignment
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This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:
1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`
Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.
Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
2026-03-04 21:34:40 -08:00
Akash Levy
a67471d7f9
Merge pull request #115 from Silimate/sat_clkgate
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Sat clkgate
2026-03-04 18:02:27 -08:00
YRabbit
26dc01102e
GOWIN. Disable read-before-write mode.
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According to the latest documentation from GOWIN -
"UG285-1.4E Gowin BSRAM & SSRAM User Guide"
The dual port BSRAM of all 55nm devices (including GW1N, GW2A and GW1A
series) does not support the read-before-write mode (WRITE_MODE = 2)
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2026-03-05 09:17:37 +10:00
Akash Levy
e765688cb7
Merge pull request #118 from Silimate/autoscope
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Autoscope supports top-level fork scope ports
2026-03-04 15:06:41 -08:00
AdvaySingh1
e2b71b0d55
Added -word arg
2026-03-04 14:51:47 -08:00
abhinavputhran
94c789e9c8
setundef: respect selection for cells, processes, and connections
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Previously, setundef would rewrite sigspecs in all cells, processes,
and connections regardless of the active selection. Only modules and
memories were correctly filtered by selection.
Fix by using module->selected_cells() for cells, adding a
module->selected() check for processes, and checking wire selection
on the lhs of each connection before rewriting.
Fixes #5624
2026-03-04 17:48:35 -05:00
AdvaySingh1
2836cc8f25
Added test cases for the infer_ce pass
2026-03-04 12:03:38 -08:00
AdvaySingh1
26adc17fd7
Revert "Changed to for chacterization"
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Removing changing _DFF_ to dff for chacterization
2026-03-04 10:43:53 -08:00
Emil J. Tywoniak
39343f5f33
docs: document S&R undefined for $dffsr and $dffsre
2026-03-04 19:39:41 +01:00
Stan Lee
a01d0b2935
autoscope supports top-level fork scope ports
2026-03-04 10:25:53 -08:00
Emil J
0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes
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celltypes: compile-time lookup tables for internal cells
2026-03-04 14:47:57 +00:00
Emil J. Tywoniak
6485a13809
newcelltypes: mark header unstable
2026-03-04 15:17:26 +01:00
Miodrag Milanović
3bc26ff4d0
Merge pull request #5723 from YosysHQ/micko/merge_queue
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CI: add support for merge queue
2026-03-04 13:18:09 +01:00
nella
16b1a914f1
Aiger use defines for known ops.
2026-03-04 12:39:45 +01:00
nella
04822c6660
Readd builtin_ff_cell_types for plugin parity.
2026-03-04 12:39:45 +01:00
nella
b8ee0803ab
Remove todo.
2026-03-04 12:39:45 +01:00
nella
66bd4716cf
rtlil use newcelltypes.
2026-03-04 12:39:45 +01:00
nella
cae54a4c7b
Aiger use newcelltypes.
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
6d4736269b
newcelltypes: extend testing
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
0284595e9c
celltypes: fix absurd eval declarations
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
793a3513c6
newcelltypes: use unordered_map
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ae10e9e955
pyosys: disable test
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
661fcb24cb
newcelltypes: fix MSVC build
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
f594014bef
newcelltypes: proper bounds for unit test
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
12412d1fa5
register: use newcelltypes
2026-03-04 12:39:45 +01:00
Emil J. Tywoniak
ecb8b20f62
yosys: use newcelltypes for yosys_celltypes users
2026-03-04 12:39:44 +01:00
Emil J. Tywoniak
5216d32d1b
yosys: use newcelltypes for yosys_celltypes
2026-03-04 12:22:47 +01:00
Emil J. Tywoniak
7a5c303ccd
backends: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
c3ed884bc4
drivertools: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
665b6eeb4a
aiger2: add TODO
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
4ab22cbb97
abc: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
d91e1c8607
newcelltypes: test against builtin_ff_cell_types
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
31b86ebc2e
newcelltypes: comment
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
8e17fb0266
consteval: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a0f87dc2d1
modtools: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a9463d1aee
newcelltypes: fix non-cells
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
e3f9911e33
newcelltypes: refactor
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
07ec8708e4
share: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
3212dfaf1f
newcelltypes: fix unit test
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
2d7d6ca10b
newcelltypes: unit test
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
7e9e88c2ec
newcelltypes: bounds check
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
9e59f05c25
newcelltypes: wrap design celltypes support
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
35ccaa60d7
newcelltypes: TurboCellTypes -> StaticCellTypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
6adc08b0e5
opt_expr: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
3671d577a0
opt_clean: use newcelltypes
2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
a61455645d
newcelltypes: init
2026-03-04 12:22:14 +01:00
Miodrag Milanovic
cf4d4ff23d
CI: add support for merge queue
2026-03-04 11:35:16 +01:00
Miodrag Milanović
05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix
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abc9: preserve topological-loop asserts with targeted SCC fallback
2026-03-04 11:09:38 +01:00
