Emil J. Tywoniak
31fde78a09
rtlil: replace SigSig actions with new type SyncAction
2025-12-10 18:32:39 +01:00
Emil J
46fbed6e6f
Merge pull request #5525 from YosysHQ/emil/fix-xaiger2-empty-cell-input
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aiger2: fix empty cell input
2025-12-04 16:47:53 +01:00
Gus Smith
dd65dd610d
Fixes
2025-12-02 11:17:21 -08:00
Emil J. Tywoniak
b2270ae1c8
aiger2: fix case where submodule cell input port has empty SigSpec
2025-12-01 19:40:58 +01:00
Emil J. Tywoniak
cebb80250c
aiger2: formatting
2025-12-01 19:40:17 +01:00
Gus Smith
ade6379345
Explicitly store whether to use association lists
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Instead of checking for the presence of helper names each time we need to
determine whether to use association lists, explicitly store a boolean flag
indicating whether association list helpers are being used.
2025-11-29 15:24:56 -08:00
Gus Smith
ddcd93024f
Capture error case more correctly
2025-11-29 15:20:37 -08:00
Gus Smith
ded7c9cb03
More formatting undos'
2025-11-29 14:59:04 -08:00
Gus Smith
9909049d2a
Undo formatting changes
2025-11-29 14:55:55 -08:00
Gus Smith
6fe35fa46c
Merge remote-tracking branch 'origin/main' into gussmith23-rosette-backend-updates
2025-11-29 14:20:36 -08:00
Robert O'Callahan
b870693393
Fix reset_auto_counter_id to correctly detect _NNN_ patterns
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This fixes a regression caused by commit c4c389fdd7
2025-11-17 09:21:59 +00:00
Robert O'Callahan
c4c389fdd7
Fix verilog backend to avoid IdString::c_str()
2025-11-12 11:52:04 +01:00
KrystalDelusion
529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params
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Handle unsized params
2025-11-12 07:14:44 +13:00
Robert O'Callahan
92ea557979
Build a temporary SigChunk list in the iterator in the cases where that's needed
2025-11-07 15:54:55 +00:00
Krystine Sherwin
7302bf9a66
Add CONST_FLAG_UNSIZED
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In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
2025-11-07 17:45:07 +13:00
KrystalDelusion
52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor
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Refactor getting dirs and filenames from paths to files
2025-11-05 09:12:54 +13:00
Emil J. Tywoniak
5cfe6a9c1e
reduce OS ifdefs, refactor getting dirs and filenames from paths to files
2025-10-14 15:46:17 +02:00
Krystine Sherwin
1a0b5d8ea7
write_btor: Include $assert and $assume cells in -ywmap output
2025-10-09 14:50:36 +02:00
Jannis Harder
90669ab4eb
aiger2: Only fail for reachable undirected bufnorm helper cells
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The aiger2 backend checks for unsupported cells during indexing. This
causes it to fail when `$connect` or `$tribuf` (as workaround for
missing 'z-$buf support) cells are present in the module.
Since bufnorm adds these cells automatically, it is very easy to end up
with them due to unconnected wires or e.g. `$specify` cells, which do
not pose an actual problem for the backend, since it will never
encounter those during a traversal.
With this, we ignore them during indexing and only produce an actual error
message if we reach such a cell during the traversal.
2025-09-29 08:21:28 +02:00
Robert O'Callahan
1e5f920dbd
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
Emil J
a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
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write_rtlil: don't sort
2025-09-22 11:14:39 +02:00
Jannis Harder
79e05a195d
verilog: Bufnorm cell backend and frontend support
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This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
Jannis Harder
47b3ee8c8b
write_aiger2: Ignore the $input_port cell during indexing.
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The $input_port cell is added by the bufnorm code to simplify handling
of input ports for new code that uses bufnorm, but the aiger2 backend
does already handle input ports separately, so we just ignore those.
2025-09-17 13:56:46 +02:00
Jannis Harder
4918f37be3
write_aiger2: Treat inout ports as output ports
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With the previous bufnorm implementation inout ports were not supported
at all, so this didn't matter, but with the new bufnorm implementation
they need to be treated as output ports.
2025-09-17 13:56:46 +02:00
Jannis Harder
6466b15367
Merge pull request #5351 from jix/xaiger_ponum_fix
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write_xaiger2: Fix output port mapping when opaque boxes are present
2025-09-17 13:56:21 +02:00
Jannis Harder
2d81726459
write_xaiger2: Fix output port mapping when opaque boxes are present
2025-09-17 13:10:04 +02:00
Emil J
73e47ac3fe
Merge pull request #5357 from rocallahan/builtin-ff
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Instead of using `builtin_ff_cell_types()` directly, go through a method `Cell::is_builtin_ff()`
2025-09-17 11:37:16 +02:00
Robert O'Callahan
d24488d3a5
Instead of using builtin_ff_cell_types() directly, go through a method Cell::is_builtin_ff()
2025-09-17 03:24:19 +00:00
Robert O'Callahan
f80be49fa1
Remove unnecessary .c_str() in EDIF_ macros
2025-09-16 23:14:11 +00:00
Robert O'Callahan
a1141f1a4c
Remove some unnecessary .c_str() calls to the result of unescape_id()
2025-09-16 23:12:14 +00:00
Robert O'Callahan
a7c46f7b4a
Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()
2025-09-16 23:02:16 +00:00
Robert O'Callahan
5ac6858f26
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
Emil J. Tywoniak
bcc69d5f6e
write_rtlil: add -sort to match old behavior
2025-09-16 15:47:16 +02:00
Emil J. Tywoniak
1328a33e82
write_rtlil: dump in insertion order
2025-09-16 15:47:14 +02:00
Emil J. Tywoniak
430adb3b59
write_rtlil: don't sort
2025-09-16 15:39:12 +02:00
Robert O'Callahan
34df6569a6
Update backends to avoid bits()
2025-09-16 03:17:23 +00:00
Jannis Harder
193b057983
Merge pull request #5341 from rocallahan/more-varargs-conversion
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More varargs conversion
2025-09-12 18:09:42 +02:00
Robert O'Callahan
ff5177ce8e
Remove .c_str() from parameters to btorf() and infof()
2025-09-12 05:53:59 +00:00
Robert O'Callahan
6f0c8f56a3
Convert btorf()/infof() to C++ stringf machinery
2025-09-12 05:53:19 +00:00
Robert O'Callahan
e0ae7b7af4
Remove .c_str() calls from log()/log_error()
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There are some leftovers, but this is an easy regex-based approach that removes most of them.
2025-09-11 20:59:37 +00:00
Robert O'Callahan
d34ac0c87d
Make log() use the FmtString infrastructure.
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Now `log()` supports `std::string`.
We have to fix a few places where the format parameter was not a compile time constant.
This is mostly trivial.
2025-09-09 15:41:03 +02:00
Robert O'Callahan
c7df6954b9
Remove .c_str() from stringf parameters
2025-09-01 23:34:42 +00:00
Jannis Harder
41452e43b2
Merge pull request #4475 from georgerennie/skip_cover
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smtbmc: Support skipping steps in cover mode
2025-09-01 13:53:04 +02:00
Jannis Harder
501bf4ce40
Merge pull request #4711 from georgerennie/george/btor_buf
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write_btor: support $buf
2025-09-01 13:38:25 +02:00
Robert O'Callahan
e0e70d1158
Remove some c_str() calls where they're no longer needed as parameters to stringf().
2025-08-18 14:20:31 +01:00
Hongce Zhang
76e507f307
update verilog_backend according to Github comments
2025-08-08 16:17:37 +08:00
Hongce Zhang
b635ab72bf
Merge branch 'main' of github.com:zhanghongce/yosys
2025-08-07 11:37:55 +08:00
Hongce Zhang
3cbbb9456d
reorder verilog backend port wires
2025-08-07 11:37:23 +08:00
Krystine Sherwin
3959d19291
Reapply "Add groups to command reference"
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This reverts commit 81f87ce6ed
2025-08-06 13:52:12 +12:00
Miodrag Milanović
1d229ae254
Merge pull request #5221 from rocallahan/typed-stringf
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Introduce variadic template implementation of `stringf` that supports `std::string` parameters
2025-07-29 15:12:49 +02:00
