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8417 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init 
In sat: 'x' in init attr should be ignored
 2019-08-28 00:18:14 +02:00
Marcin Kościelnicki
d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
Eddie Hung
eab3c1432b
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap 
Add clock buffer insertion pass, improve iopadmap.
 2019-08-27 10:19:27 -07:00
Eddie Hung
28133432be Ignore all 1'bx in (* init *) 2019-08-27 09:24:59 -07:00
Eddie Hung
00387f3927 Revert to using clean 2019-08-27 09:24:32 -07:00
SergeyDegtyar
980830f7b8 Revert "Add tests for ecp5 architecture." 
This reverts commit 134d3fea90.
 2019-08-27 18:28:05 +03:00
Marcin Kościelnicki
5fb4b12cb5 improve clkbuf_inhibit propagation upwards through hierarchy 2019-08-27 17:26:47 +02:00
SergeyDegtyar
134d3fea90 Add tests for ecp5 architecture. 2019-08-27 18:12:18 +03:00
David Shah
fc001b4731 ecp5: Add GSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:07:06 +01:00
SergeyDegtyar
aad9bad326 Add tests for macc and rom; 
Test cases from
https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071;
In both cases synthesized only LUTs and DFFs.
 2019-08-27 13:56:26 +03:00
Clifford Wolf
fdbcf78909 Add "make bumpversion" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-27 10:15:25 +02:00
Eddie Hung
9172d4a674 Missing close bracket 2019-08-26 21:02:52 -07:00
Eddie Hung
6b5e65919a Revert "In sat: 'x' in init attr should not override constant" 
This reverts commit 2b37a093e9.
 2019-08-26 17:52:57 -07:00
Eddie Hung
54422c5bb4 Remove leftover header 2019-08-26 17:51:13 -07:00
Eddie Hung
e95fb24574 Improve xilinx_srl.fixed generate, add .variable generate 2019-08-26 17:49:08 -07:00
Eddie Hung
45c34c87ee Account for maxsubcnt overflowing 2019-08-26 17:48:54 -07:00
Eddie Hung
b32d6bf403 Add xilinx_srl_pm.variable to test_pmgen 2019-08-26 17:44:57 -07:00
Eddie Hung
e574edc3e9 Populate generate for xilinx_srl.fixed pattern 2019-08-26 14:21:17 -07:00
Eddie Hung
cf9e017127 Add xilinx_srl_fixed, fix typos 2019-08-26 14:20:06 -07:00
Eddie Hung
1ba09c4ab7 Merge branch 'master' into eddie/xilinx_srl 2019-08-26 13:56:31 -07:00
Eddie Hung
528f1c8687 Improve tests to check that clkbuf is connected to expected 2019-08-26 13:45:16 -07:00
Eddie Hung
a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung
bd3773a17f Remove dupe in CHANGELOG, missing end quote 2019-08-26 10:44:23 -07:00
Clifford Wolf
8a4c6e6563 Merge tag 'yosys-0.9' 2019-08-26 11:14:22 +02:00
Clifford Wolf
1979e0b1f2 Yosys 0.9 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-26 10:37:53 +02:00
Clifford Wolf
a3de83ef4a
Merge pull request #1112 from acw1251/pyosys_sigsig_issue 
Fixed pyosys commands returning RTLIL::SigSig
 2019-08-25 11:22:02 +02:00
Eddie Hung
dc87372a97 Wire with init on FF part, 1'bx on non-FF part 2019-08-24 15:05:44 -07:00
Clifford Wolf
dc9c47b5af
Merge pull request #1327 from YosysHQ/clifford/pmgen 
Add pmgen slices and choices
 2019-08-24 08:38:49 +02:00
Eddie Hung
7911143827 Create new $__XILINX_SHREG_ cell for variable length too 2019-08-23 18:15:49 -07:00
Eddie Hung
a048fc93e8 Do not allow Q of last cell of variable length SRL to be (* keep *) 2019-08-23 18:15:24 -07:00
Eddie Hung
ee9f6e6243 Also add first.Q to chain_bits since variable length 2019-08-23 18:14:06 -07:00
Eddie Hung
70ce3d0670 Do not enforce !EN_POLARITY on $dffe 2019-08-23 18:11:28 -07:00
Eddie Hung
188b49378a Create new cell for fixed length SRL 2019-08-23 17:25:30 -07:00
Eddie Hung
e081303ee8 Cleanup FDRE matching 2019-08-23 17:23:52 -07:00
Eddie Hung
d7051b90de Add undocumented feature 2019-08-23 16:41:32 -07:00
Eddie Hung
54488cfb82 Oops don't need a finally block 2019-08-23 16:39:37 -07:00
Eddie Hung
83e2d87fb8 Keep track of bits in variable length chain, to check for taps 2019-08-23 16:21:10 -07:00
Eddie Hung
f2d4814284 Don't forget $dff has no EN 2019-08-23 16:14:57 -07:00
Eddie Hung
2217d926a9 Same for variable length 2019-08-23 16:13:16 -07:00
Eddie Hung
b1caf7be5e Filter on en_port for fixed length 2019-08-23 16:09:46 -07:00
Eddie Hung
513af10d77 Check clock is consistent 2019-08-23 15:18:26 -07:00
Eddie Hung
c762618783 Fix last_cell.D 2019-08-23 15:08:49 -07:00
Eddie Hung
ca5de78e76 Revert "Add a unique argument to pmgen's nusers()" 
This reverts commit 1d88887cfd.
 2019-08-23 15:04:00 -07:00
Eddie Hung
e85e6e8d45 Revert "Fix polarity" 
This reverts commit 9cd23cf0fe.
 2019-08-23 15:03:42 -07:00
Eddie Hung
9cd23cf0fe Fix polarity 2019-08-23 14:49:34 -07:00
Eddie Hung
c2757613b6 Check for non unique nusers/fanouts 2019-08-23 14:32:36 -07:00
Eddie Hung
1d88887cfd Add a unique argument to pmgen's nusers() 2019-08-23 14:32:17 -07:00
Eddie Hung
8ecfd55d5a Update doc 2019-08-23 14:16:41 -07:00
Eddie Hung
3d7f4aa0c8 Remove (* init *) entry when consumed into SRL 2019-08-23 13:56:01 -07:00
Eddie Hung
3fa826254f Merge branch 'xaig_arrival' of github.com:YosysHQ/yosys into xaig_arrival 2019-08-23 13:46:17 -07:00