126 commits

Author	SHA1	Message	Date
Eddie Hung	5aef998957	Add more comments	2019-08-09 09:48:17 -07:00
Eddie Hung	dae7c59358	Add a few comments to document $alu and $lcu	2019-08-08 10:05:28 -07:00
Clifford Wolf	64925b4e8f	Improve $specrule interface ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 22:57:10 +02:00
Clifford Wolf	4575e4ad86	Improve $specrule interface ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 22:18:04 +02:00
Clifford Wolf	71c38d9de5	Add $specrule cells for $setup/$hold/$skew specify rules ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	e807e88b60	Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	a7e11261bd	Add $specify2 and $specify3 cells to simlib ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-04-23 21:36:59 +02:00
Clifford Wolf	eb67a7532b	Add $allconst and $allseq cell types ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-02-23 13:14:47 +01:00
Clifford Wolf	5f1d0b1024	Add $live and $fair cell types, add support for s_eventually keyword	2017-02-25 10:36:39 +01:00
Clifford Wolf	3928482a3c	Add $cover cell type and SVA cover() support	2017-02-04 14:14:26 +01:00
Clifford Wolf	bdc316db50	Added $anyseq cell type	2016-10-14 15:24:03 +02:00
Clifford Wolf	53655d173b	Added $global_clock verilog syntax support for creating $ff cells	2016-10-14 12:33:56 +02:00
Clifford Wolf	8ebba8a35f	Added $ff and $_FF_ cell types	2016-10-12 01:18:39 +02:00
Clifford Wolf	6f41e5277d	Removed $aconst cell type	2016-08-30 19:09:56 +02:00
Clifford Wolf	eae390ae17	Removed $predict again	2016-08-28 21:35:33 +02:00
Clifford Wolf	4056312987	Added $anyconst and $aconst	2016-07-27 15:41:22 +02:00
Clifford Wolf	5c166e76e5	Added $initstate cell type and vlog function	2016-07-21 14:23:22 +02:00
Clifford Wolf	d7763634b6	After reading the SV spec, using non-standard predict() instead of expect()	2016-07-21 13:34:33 +02:00
Clifford Wolf	721f1f5ecf	Added basic support for $expect cells	2016-07-13 16:56:17 +02:00
Clifford Wolf	95757efb25	Improved support for $sop cells	2016-06-17 16:31:16 +02:00
Clifford Wolf	52bb1b968d	Added $sop cell type and "abc -sop"	2016-06-17 13:50:09 +02:00
Clifford Wolf	19c20235b5	Added more cell help messages	2016-03-29 15:14:43 +02:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	d5b1a90b33	Added $tribuf and $_TBUF_ sim models	2015-08-16 13:05:32 +02:00
Larry Doolittle	6c00704a5e	Another block of spelling fixes ... Smaller this time	2015-08-14 23:27:05 +02:00
Clifford Wolf	8d6d5c30d9	Added WORDS parameter to $meminit	2015-07-31 10:40:09 +02:00
Clifford Wolf	6c84341f22	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
Clifford Wolf	95944eb69e	make all vector-size related integer params in $mem sim model signed ... this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.	2015-04-05 17:26:53 +02:00
Clifford Wolf	b005eedf36	Added $assume cell type	2015-02-26 18:04:10 +01:00
Clifford Wolf	ec05242c27	Smaller default parameters in $mem simlib model	2015-02-15 00:20:05 +01:00
Clifford Wolf	dcf2e24240	Added $meminit support to "memory" command	2015-02-14 12:55:03 +01:00
Clifford Wolf	910556560f	Added $meminit cell type	2015-02-14 10:23:03 +01:00
Clifford Wolf	d58c3eca3a	Some test related fixes ... (incl. removal of three bad test cases)	2015-02-12 17:45:44 +01:00
Clifford Wolf	e13a45ae61	Added $equiv cell type	2015-01-19 11:55:05 +01:00
Clifford Wolf	a7e43ae3d9	Progress in memory_bram	2015-01-03 10:57:01 +01:00
Clifford Wolf	90f4017703	Added proper clkpol support to memory_bram	2015-01-02 22:57:08 +01:00
Clifford Wolf	474831643c	New $mem simlib model	2015-01-02 17:11:31 +01:00
Clifford Wolf	ba43cf5807	Fixed simlib entries for $memrd and $memwr	2014-12-30 13:33:29 +01:00
Clifford Wolf	f1764b4fe9	Added $dffe cell type	2014-12-08 10:50:19 +01:00
Clifford Wolf	6644e27cd4	Fixed $macc simlib model for zero-config	2014-09-16 08:19:35 +02:00
Clifford Wolf	44b5bd4b63	Fixed simlib $macc model for xilinx xsim	2014-09-08 17:09:39 +02:00
Clifford Wolf	fcb46138ce	Simplified $fa undef model	2014-09-08 16:59:39 +02:00
Clifford Wolf	6dc07eb1f2	Fixes and cleanups for blackbox.v	2014-09-08 13:31:04 +02:00
Clifford Wolf	af0c8873bb	Added $lcu cell type	2014-09-08 13:31:04 +02:00
Clifford Wolf	d46bac3305	Added "$fa" cell type	2014-09-08 12:15:39 +02:00
Clifford Wolf	9329a76818	Various bug fixes (related to $macc model testing)	2014-09-06 20:30:46 +02:00
Clifford Wolf	fa64942018	Added $macc SAT model	2014-09-06 19:44:11 +02:00
Clifford Wolf	bff4706b62	Added $macc simlib model (also use as techmap rule for now)	2014-09-06 17:59:12 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	635b922afe	Undef-related fixes in simlib $alu model	2014-09-02 23:21:59 +02:00