Claire Wolf
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2ce7a0d369
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Merge pull request #1667 from YosysHQ/clifford/verificnand
Add Verific support for OPER_REDUCE_NAND
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2020-01-30 19:55:53 +01:00 |
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Claire Wolf
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60876ce183
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Merge pull request #1503 from YosysHQ/eddie/verific_help
`verific` pass to print help message when command syntax error
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2020-01-30 18:05:16 +01:00 |
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Claire Wolf
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ffadaddab5
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Merge pull request #1654 from YosysHQ/eddie/sby_fix69
verific: unflatten struct ports
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2020-01-30 18:03:35 +01:00 |
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Claire Wolf
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23c44afaed
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Add Verific support for OPER_REDUCE_NAND
Signed-off-by: Claire Wolf <clifford@clifford.at>
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2020-01-30 18:01:13 +01:00 |
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Claire Wolf
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1679682fa3
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Merge branch 'vector_fix' of https://github.com/Kmanfi/yosys
Also some minor fixes to the original PR.
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2020-01-29 17:01:24 +01:00 |
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Claire Wolf
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4d0118d0c1
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Merge pull request #1662 from YosysHQ/dave/opt-reduce-move-check
opt_reduce: Call check() per run rather than per optimised cell
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2020-01-29 15:27:11 +01:00 |
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Claire Wolf
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bc325468e7
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Merge pull request #1665 from YosysHQ/clifford/edifkeep
Preserve wires with keep attribute in EDIF back-end
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2020-01-29 15:25:56 +01:00 |
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Claire Wolf
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5f53ea2b5b
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Merge pull request #1659 from YosysHQ/clifford/experimental
Add log_experimental() and experimental() API and "yosys -x"
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2020-01-29 15:25:03 +01:00 |
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N. Engelhardt
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177a7cb23e
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Merge pull request #1510 from pumbor/master
handle anonymous unions to fix #1080
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2020-01-29 15:21:28 +01:00 |
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Claire Wolf
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50d70288d0
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Preserve wires with keep attribute in EDIF back-end
Signed-off-by: Claire Wolf <clifford@clifford.at>
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2020-01-29 14:07:11 +01:00 |
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Miodrag Milanović
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71d148bcaa
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Merge pull request #1559 from YosysHQ/efinix_test_fix
Fix for non-deterministic test
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2020-01-29 11:18:06 +01:00 |
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Eddie Hung
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d004953772
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Add "help -all" and "help -celltypes" sanity test
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2020-01-28 18:11:34 -08:00 |
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Eddie Hung
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c5971cb16c
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synth_xilinx: cleanup help
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2020-01-28 17:48:43 -08:00 |
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Eddie Hung
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0fd64aab25
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synth_xilinx: fix help when no active_design; fixes #1664
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2020-01-28 17:41:57 -08:00 |
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Marcin Kościelnicki
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7e0e42f907
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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Eddie Hung
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a855f23f22
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Merge remote-tracking branch 'origin/master' into eddie/opt_merge_init
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2020-01-28 12:46:18 -08:00 |
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Eddie Hung
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7939727d14
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Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts
Unpermute LUT ordering for ice40/ecp5/xilinx
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2020-01-28 11:55:51 -08:00 |
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Eddie Hung
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6d27d43727
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Add and use SigSpec::reverse()
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2020-01-28 10:37:16 -08:00 |
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Eddie Hung
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245b8c4ab6
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Fix unresolved conflict from #1573
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2020-01-28 10:17:47 -08:00 |
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Miodrag Milanovic
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94191a93dd
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Updated test to use assert-max
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2020-01-28 18:26:10 +01:00 |
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Claire Wolf
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5c2508cef8
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Improve logging use of experimental features
Signed-off-by: Claire Wolf <clifford@clifford.at>
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2020-01-28 17:51:50 +01:00 |
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Claire Wolf
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4ddaa70fd6
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Merge pull request #1567 from YosysHQ/eddie/sat_init_warning
sat: suppress 'Warning: ignoring initial value on non-register: ...' when init[i] = 1'bx
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2020-01-28 17:40:28 +01:00 |
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N. Engelhardt
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086c133ea5
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Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate
synth_xilinx: error out if tristate without '-iopad'
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2020-01-28 17:24:54 +01:00 |
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David Shah
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6fd9cae5ca
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opt_reduce: Call check() per run rather than per optimised cell
Signed-off-by: David Shah <dave@ds0.me>
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2020-01-28 09:42:01 +00:00 |
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Pepijn de Vos
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409e532433
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redirect fuser stderr to /dev/null
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2020-01-28 10:02:41 +01:00 |
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Claire Wolf
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8f40113826
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Merge pull request #1553 from whitequark/manual-dffx
Document $dffe, $dffsr, $_DFFE_*, $_DFFSR_* cells
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2020-01-28 09:41:08 +01:00 |
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Eddie Hung
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21ce1b37fb
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abc9_ops: -check for negative arrival/required times
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2020-01-27 14:22:46 -08:00 |
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Eddie Hung
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e18aeda7ed
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Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards
Just like Verilog...
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2020-01-27 14:02:13 -08:00 |
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Eddie Hung
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cfb0366a18
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Import tests from #1628
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2020-01-27 13:56:16 -08:00 |
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Eddie Hung
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ce6a690d27
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xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
Now done in read_aiger
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2020-01-27 13:30:27 -08:00 |
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Eddie Hung
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48f3f5213e
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Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
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2020-01-27 13:29:15 -08:00 |
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Eddie Hung
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e0bdf5d7a9
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Fix typo
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2020-01-27 12:30:39 -08:00 |
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Eddie Hung
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f2576c096c
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Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
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2020-01-27 12:29:28 -08:00 |
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Eddie Hung
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9009b76a69
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abc9_ops: add comments
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2020-01-27 11:18:21 -08:00 |
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Eddie Hung
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f443695a38
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Merge remote-tracking branch 'origin/master' into eddie/verific_help
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2020-01-27 10:34:10 -08:00 |
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Eddie Hung
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d730bba6d2
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verific: no help() when no YOSYS_ENABLE_VERIFIC
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2020-01-27 10:32:18 -08:00 |
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Eddie Hung
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7b445121cc
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verific: also unflatten for 'hierarchy' flow as per @cliffordwolf
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2020-01-27 10:15:22 -08:00 |
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Eddie Hung
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af8281d2f5
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Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings
ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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2020-01-27 09:54:04 -08:00 |
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Claire Wolf
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cef607c8b7
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Add log_experimental() and experimental() API and "yosys -x"
Signed-off-by: Claire Wolf <clifford@clifford.at>
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2020-01-27 18:27:47 +01:00 |
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Claire Wolf
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07a12ebd4f
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Merge pull request #1658 from YosysHQ/clifford/smtbmcsolvernotfound
Improve yosys-smtbmc "solver not found" handling
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2020-01-27 17:59:58 +01:00 |
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Claire Wolf
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485f31f681
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Improve yosys-smtbmc "solver not found" handling
Signed-off-by: Claire Wolf <clifford@clifford.at>
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2020-01-27 17:48:56 +01:00 |
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Claire Wolf
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de6006fbc8
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Merge pull request #1613 from porglezomp-misc/version-flag-alias
Add --version and -version as aliases for -V
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2020-01-27 12:59:27 +01:00 |
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Eddie Hung
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c7fbe13db5
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read_aiger: set abc9_box_seq attr
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2020-01-24 13:11:43 -08:00 |
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Eddie Hung
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81e6b040a4
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ice40: add SB_SPRAM256KA arrival time
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2020-01-24 12:17:09 -08:00 |
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Eddie Hung
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b178761551
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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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2020-01-24 11:59:48 -08:00 |
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Eddie Hung
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cccc0ae112
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verific: unflatten struct ports
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2020-01-24 10:12:52 -08:00 |
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Eddie Hung
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dbf351390e
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abc9: -reintegrate recover type from existing cell, check against boxid
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2020-01-23 22:45:34 -08:00 |
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Eddie Hung
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2d795fb8c0
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simple_abc9 tests to discard whitebox before write for sim
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2020-01-23 22:07:43 -08:00 |
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Eddie Hung
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dca1c806ec
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simple_abc9 tests to discard whitebox before write for sim
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2020-01-23 19:55:11 -08:00 |
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Eddie Hung
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e471b330ac
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abc_box_id -> abc9_box_id in test
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2020-01-23 19:12:19 -08:00 |
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