Martin Povišer
4c3203866f
exec: Add missing newline
2024-08-07 13:02:00 +02:00
Emil J. Tywoniak
4b29f64142
cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
2024-07-29 10:26:02 +02:00
Martin Povišer
0cefe8a1e8
check: Skip detailed edge modeling if costly
2024-07-18 13:08:19 +02:00
Martin Povišer
e70b1251ad
check: Adjust prints
2024-07-18 13:08:19 +02:00
Martin Povišer
3f71bc469d
check: Rephrase comment
2024-07-18 13:08:19 +02:00
Miodrag Milanovic
9b82a44d25
Fix help message typo
2024-06-07 08:26:59 +02:00
Martin Povišer
4b67f3757f
Merge pull request #4404 from YosysHQ/povik/bbox_derive
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box_derive: New command to derive modules for boxes
2024-05-31 19:09:18 +02:00
Martin Povišer
b230c95cc4
select: Adjust help
2024-05-29 20:41:56 +02:00
Martin Povišer
49906be776
select: Introduce -assert-mod-count
2024-05-21 16:34:38 +02:00
Martin Povišer
adc1a01490
select: Refactor some flag validation
2024-05-21 16:29:20 +02:00
Martin Povišer
c0a196173a
Rename bbox_derive to box_derive
2024-05-21 16:18:03 +02:00
Martin Povišer
5c929a91c2
bbox_derive: Write help
2024-05-21 14:57:37 +02:00
Martin Povišer
88af059fad
bbox_derive: Fix done base type confusion
2024-05-21 14:57:26 +02:00
Emil J. Tywoniak
44b0fdc2bf
bbox_derive: add assert and debug print
2024-05-03 20:43:01 +02:00
Emil J. Tywoniak
e8c58a5528
bbox_derive: fix unininitialized memory UB when run with no named args
2024-05-03 20:41:42 +02:00
Martin Povišer
4c000d3aba
Add new bbox_derive command for blackbox derivation
2024-05-03 20:39:11 +02:00
Martin Povišer
b00abe4a26
Extend log command with -push, -pop, -header options
2024-04-10 11:49:20 +02:00
Martin Povišer
47931f9050
Merge pull request #4295 from gadfort/add-ports-stat
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add port statistics to stat command
2024-04-08 11:12:02 +02:00
Peter Gadfort
160e3e089a
add port statistics to stat command
2024-03-22 09:20:20 -04:00
Martin Povišer
206d894c56
check: Omit private wires in loop report
2024-03-11 10:45:36 +01:00
Martin Povišer
d01728aaa5
celledges: Register async FF paths
2024-03-11 10:45:36 +01:00
Martin Povišer
4fdcf388d3
check: Assert edges data is not out-of-bounds
2024-03-11 10:45:17 +01:00
Martin Povišer
b6112b3551
check: Consider read ports in loop detection
2024-03-11 10:45:17 +01:00
Martin Povišer
fa74d0bd1a
check: Use cell edges data in detecting combinational loops
2024-03-11 10:43:49 +01:00
Martin Povišer
c5ae74af34
check: Improve found loop logging
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Print the detected loop in-order, and include source location for each
node, if available.
2024-03-11 10:43:49 +01:00
Jannis Harder
d8cdc213a6
rename -witness: Bug fix and rename formal cells
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Rename formal cells in addition to witness signals. This is required to
reliably track individual property states for the non-smtbmc flows.
Also removes a misplced `break` which resulted in only partial witness
renaming.
2024-03-04 16:53:03 +01:00
Miodrag Milanović
a3c81f4d62
Merge pull request #4216 from YosysHQ/show_href
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show: Add option to add cell/wire "src" attribute into graphviz attribute href
2024-02-19 20:50:53 +01:00
N. Engelhardt
4b99db0b73
Merge pull request #4177 from povik/connect-extra_args
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connect: Do interpret selection arguments
2024-02-19 15:18:37 +01:00
Ethan Mahintorabi
b8a1009de9
Update passes/cmds/stat.cc
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Make reporting line more clear about the non cumulative area of sequential cells
Co-authored-by: N. Engelhardt <nakengelhardt@gmail.com>
2024-02-16 07:44:09 -08:00
Ethan Mahintorabi
f0df0e3912
update type and variable names
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Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-16 00:01:44 +00:00
Ethan Mahintorabi
2d8343d423
update type and variable names
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Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-15 23:59:19 +00:00
Miodrag Milanovic
834276a2f7
show: Add option to add cell/wire "src" attribute into graphviz attribute href
2024-02-14 09:50:53 +01:00
Ethan Mahintorabi
8566489d85
stat: Add sequential area output to stat -liberty
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Checks to see if a cell is of type ff in the liberty,
and keeps track of an additional area value.
```
Chip area for module '\addr': 92.280720
Sequential area for module '\addr': 38.814720
```
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-09 23:51:00 +00:00
Claire Xen
1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite
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Add API to overwrite existing pass from plugin
2024-02-05 23:49:24 +01:00
Jannis Harder
6c4902313b
chformal: Support $check cells and add chformal -lower
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This adds support for `$check` cells in chformal and adds a `-lower`
mode which converts `$check` cells into `$assert` etc. cells with a
`$print` cell to output the `$check` message.
2024-02-01 20:10:39 +01:00
Martin Povišer
a84fa0a277
connect: Do interpret selection arguments
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Instead of silently ignoring what would ordinarily be the selection
arguments to a pass, interpret those and mark the support in the help
message.
2024-02-01 10:28:36 +01:00
Claire Xenia Wolf
4fa314c0bd
Add API to overwrite existing pass from plugin
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-01-30 17:51:11 +01:00
Stephen Tong
b3e7390c0e
Fix typo in stat help
2024-01-21 16:32:05 -05:00
N. Engelhardt
fb4eeb1344
show: allow setting colors via selection on PROC boxes
2024-01-15 17:47:59 +01:00
Lofty
d21c464ae4
Merge pull request #3946 from rmlarsen/toposort
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Speed up TopoSort by 2.7-3.3x.
2023-10-17 13:00:18 +01:00
Marcus Comstedt
0ca39e233b
scc: Use hashlib instead of STL for deterministic behaviour
2023-10-07 10:43:00 +02:00
Rasmus Munk Larsen
0a37c2a301
Fix translation bug: The old code really checks for the presense of a node, not an edge in glift and flatten.
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Add back statement that inserts nodes in order in opt_expr.cc.
2023-10-05 17:01:42 -07:00
Jannis Harder
5daa49bafb
dft_tag: Fix size extending $x[n]or and $reduce_{or,bool}/$logic_not
2023-09-28 17:33:55 +02:00
N. Engelhardt
3319fdc46e
show: use dot for wire aliases instead of BUF
2023-09-25 17:20:16 +02:00
Rasmus Munk Larsen
9ed38bf9b6
Speed up the autoname pass by 3x. ( #3945 )
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* Speed up the autoname pass by 2x. This is accomplished by only constructing IdString objects for plain strings that have a higher score.
* Defer creating IdStrings even further. This increases the speedup to 3x.
2023-09-21 09:46:49 +00:00
Rasmus Munk Larsen
e0042bdff7
Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%.
2023-09-20 15:49:05 -07:00
Jannis Harder
62b4df4989
dft_tag: Implement $overwrite_tag and $original_tag
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This does not correctly handle an `$overwrite_tag` on a module output,
but since we currently require the user to flatten the design for
cross-module dft, this cannot be observed from within the design, only
by manually inspecting the signals in the design.
2023-09-13 11:32:36 +02:00
Jannis Harder
46a35da28c
Add future pass to resolve $future_ff cells
2023-09-13 11:32:36 +02:00
Jannis Harder
7a0c37b62d
Initial dft_tag implementation
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This is still missing a mode to rewrite $overwrite_tag and $original_tag
by injecting $set_tag and $get_tag in the right places. It's also
missing bit-precise propagation models for shifts and arithmetic and
requires the design to be flattened.
2023-09-13 11:32:36 +02:00
Jannis Harder
e187fc915e
xprop: Fix polarity errors and generate hdlnames
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* Fixes a non-deterministic polarity error for $eqx/$nex cells
* Fixes a deterministic polarity error for $_NOR_ and $_ORNOT_ cells
* Generates hdlnames when xprop is run after flatten
2023-09-06 19:25:47 +02:00
