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https://github.com/YosysHQ/yosys
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Initial dft_tag implementation
This is still missing a mode to rewrite $overwrite_tag and $original_tag by injecting $set_tag and $get_tag in the right places. It's also missing bit-precise propagation models for shifts and arithmetic and requires the design to be flattened.
This commit is contained in:
Jannis Harder
parent
27ac912709
commit
7a0c37b62d
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@ -46,3 +46,4 @@ OBJS += passes/cmds/printattrs.o
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OBJS += passes/cmds/sta.o
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OBJS += passes/cmds/clean_zerowidth.o
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OBJS += passes/cmds/xprop.o
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OBJS += passes/cmds/dft_tag.o
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932
passes/cmds/dft_tag.cc
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932
passes/cmds/dft_tag.cc
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@ -0,0 +1,932 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2022 Jannis Harder <jix@yosyshq.com> <me@jix.one>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/celltypes.h"
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#include "kernel/ff.h"
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#include "kernel/modtools.h"
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#include "kernel/sigtools.h"
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#include "kernel/yosys.h"
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#include <deque>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct DftTagOptions {
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bool tag_public;
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};
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struct DftTagWorker {
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Module *module;
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DftTagOptions options;
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ModWalker modwalker;
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SigMap &sigmap;
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FfInitVals initvals;
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struct tag_set {
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int index = 0;
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tag_set(int index = 0) : index(index) {}
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bool operator<(const tag_set &other) const { return index < other.index; }
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bool operator==(const tag_set &other) const { return index == other.index; }
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unsigned int hash() const { return hash_ops<int>::hash(index); }
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bool empty() const { return index == 0; }
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};
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idict<pool<IdString>> tag_sets;
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pool<IdString> tmp_tag_set;
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dict<std::pair<tag_set, tag_set>, tag_set> tag_set_union_cache;
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dict<SigBit, tag_set> tagged_signals;
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dict<IdString, pool<IdString>> tag_groups;
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dict<IdString, IdString> group_of_tag;
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pool<IdString> all_tags;
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pool<Cell *> pending_cells;
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std::deque<Cell *> pending_cell_queue;
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dict<std::pair<IdString, SigBit>, SigBit> tag_signals;
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// Uses SigSpec instead of SigBit so we can use coarse grained cells to combine the individual tags
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dict<std::pair<IdString, SigSpec>, SigSpec> tag_group_signals;
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pool<Cell *> warned_cells;
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DftTagWorker(Module *module, DftTagOptions options) :
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module(module), options(options), modwalker(module->design), sigmap(modwalker.sigmap)
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{
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modwalker.setup(module);
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initvals.set(&modwalker.sigmap, module);
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tag_sets(tmp_tag_set);
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}
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const pool<IdString> &tag_pool(tag_set set) { return tag_sets[set.index]; }
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tag_set singleton(IdString tag)
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{
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tmp_tag_set.clear();
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tmp_tag_set.emplace(tag);
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return tag_sets(tmp_tag_set);
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}
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tag_set merge(tag_set a, tag_set b)
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{
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if (b < a)
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std::swap(a, b);
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if (a.empty() || a == b)
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return b;
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auto found = tag_set_union_cache.find(std::make_pair(a, b));
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if (found == tag_set_union_cache.end()) {
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tmp_tag_set.clear();
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auto &a_tags = tag_pool(a);
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auto &b_tags = tag_pool(b);
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tmp_tag_set.insert(a_tags.begin(), a_tags.end());
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tmp_tag_set.insert(b_tags.begin(), b_tags.end());
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tag_set result = tag_sets(tmp_tag_set);
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tag_set_union_cache.emplace(std::make_pair(a, b), result);
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return result;
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}
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return found->second;
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}
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tag_set tags(SigBit bit)
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{
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sigmap.apply(bit);
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auto found = tagged_signals.find(bit);
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if (found != tagged_signals.end())
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return found->second;
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return tag_set();
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}
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tag_set tags(SigSpec sig)
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{
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tag_set result;
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for (auto bit : sig)
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result = merge(result, tags(bit));
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return result;
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}
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tag_set tags(Cell *cell)
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{
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tag_set result;
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for (auto &conn : cell->connections()) {
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if (cell->input(conn.first))
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result = merge(result, tags(conn.second));
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}
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return result;
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}
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void add_tags(SigBit bit, tag_set new_tags)
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{
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sigmap.apply(bit);
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auto &tags = tagged_signals[bit];
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tag_set merged_tags = merge(tags, new_tags);
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if (merged_tags == tags)
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return;
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tags = merged_tags;
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auto it = modwalker.signal_consumers.find(bit);
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if (it == modwalker.signal_consumers.end())
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return;
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for (auto &consumer : it->second)
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if (pending_cells.insert(consumer.cell).second)
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pending_cell_queue.push_back(consumer.cell);
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}
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void add_tags(SigSpec sig, tag_set new_tags)
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{
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for (auto bit : sigmap(sig))
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add_tags(bit, new_tags);
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}
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void add_tags(Cell *cell, tag_set new_tags)
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{
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for (auto &conn : cell->connections())
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if (cell->output(conn.first))
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add_tags(conn.second, new_tags);
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}
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void forward_tags(SigSpec dst, SigSpec src)
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{
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log_assert(GetSize(dst) == GetSize(src));
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for (int i = 0; i < GetSize(dst); i++)
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add_tags(dst[i], tags(src[i]));
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}
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void propagate_tags()
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{
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for (auto cell : module->cells()) {
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if (cell->type == ID($set_tag)) {
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pending_cells.insert(cell);
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pending_cell_queue.push_back(cell);
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}
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}
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while (!pending_cell_queue.empty()) {
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Cell *cell = pending_cell_queue.front();
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pending_cell_queue.pop_front();
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pending_cells.erase(cell);
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propagate_tags(cell);
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}
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}
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SigBit tag_signal(IdString tag, SigBit bit)
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{
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sigmap.apply(bit);
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if (!bit.is_wire())
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return State::S0; // Constant value - no tags
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auto found = tag_signals.find(std::make_pair(tag, bit));
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if (found != tag_signals.end())
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return found->second;
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if (!tag_pool(tags(bit)).count(tag))
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return State::S0; // Statically known to not have this tag
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// TODO handle module inputs
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auto drivers = modwalker.signal_drivers.find(bit);
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if (drivers == modwalker.signal_drivers.end() || drivers->second.empty())
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return State::S0; // No driver - no tags
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log_assert(drivers->second.size() == 1);
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auto driver = *drivers->second.begin();
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emit_tag_signals(tag, driver.cell);
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found = tag_signals.find(std::make_pair(tag, bit));
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log_assert(found != tag_signals.end());
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return found->second;
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}
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SigSpec tag_signal(IdString tag, SigSpec sig)
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{
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SigSpec result;
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for (auto bit : sig)
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result.append(tag_signal(tag, bit));
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return result;
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}
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SigSpec tag_group_signal(IdString tag_group, SigSpec sig)
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{
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sigmap.apply(sig);
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if (sig.is_fully_const() || tag_groups.count(tag_group) == 0)
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return Const(0, GetSize(sig));
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auto found = tag_group_signals.find(std::make_pair(tag_group, sig));
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if (found != tag_group_signals.end())
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return found->second;
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SigSpec combined;
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for (auto &tag : tag_groups[tag_group]) {
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auto tag_sig = tag_signal(tag, sig);
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if (!GetSize(combined))
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combined = tag_sig;
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else
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combined = autoOr(NEW_ID, combined, tag_sig);
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}
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if (!GetSize(combined))
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combined = Const(0, GetSize(sig));
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tag_group_signals.emplace(std::make_pair(tag_group, sig), combined);
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return combined;
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}
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void emit_tag_signal(IdString tag, SigBit bit, SigBit tag_bit)
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{
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sigmap.apply(bit);
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sigmap.apply(tag_bit);
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if (!tag_pool(tags(bit)).count(tag))
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return;
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auto key = std::make_pair(tag, bit);
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auto found = tag_signals.find(key);
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if (found != tag_signals.end()) {
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module->connect(found->second, tag_bit);
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return;
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}
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tag_signals.emplace(key, tag_bit);
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}
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void emit_tag_signal(IdString tag, SigSpec sig, SigSpec tag_sig)
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{
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log_assert(GetSize(sig) == GetSize(tag_sig));
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for (int i = 0; i < GetSize(sig); i++)
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emit_tag_signal(tag, sig[i], tag_sig[i]);
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}
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void emit_tag_signals(IdString tag, Cell *cell)
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{
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if (!pending_cells.insert(cell).second) {
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// We have a cycle, emit placeholder wires which will be connected
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// when the outer call for this tag/cell returns
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for (auto &conn : cell->connections())
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if (cell->output(conn.first))
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emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second)));
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return;
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}
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process_cell(tag, cell);
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pending_cells.erase(cell);
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}
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void propagate_tags(Cell *cell)
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{
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if (cell->type == ID($set_tag)) {
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IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
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if (all_tags.insert(tag).second) {
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auto group_sep = tag.str().find(':');
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IdString tag_group = group_sep != std::string::npos ? tag.str().substr(0, group_sep) : tag;
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tag_groups[tag_group].insert(tag);
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group_of_tag[tag] = tag_group;
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}
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auto &sig_y = cell->getPort(ID::Y);
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auto &sig_a = cell->getPort(ID::A);
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// TODO handle constant set/clr masks
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add_tags(sig_y, singleton(tag));
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forward_tags(sig_y, sig_a);
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return;
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}
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if (cell->type == ID($get_tag)) {
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return;
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}
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if (cell->type.in(ID($not), ID($pos))) {
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auto &sig_y = cell->getPort(ID::Y);
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auto sig_a = cell->getPort(ID::A);
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if (cell->type.in(ID($not), ID($or))) {
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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}
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forward_tags(sig_y, sig_a);
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return;
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}
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) {
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auto &sig_y = cell->getPort(ID::Y);
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auto sig_a = cell->getPort(ID::A);
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auto sig_b = cell->getPort(ID::B);
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if (cell->type.in(ID($and), ID($or))) {
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
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}
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forward_tags(sig_y, sig_a);
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forward_tags(sig_y, sig_b);
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return;
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}
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if (cell->type.in(ID($mux), ID($bwmux))) {
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auto &sig_y = cell->getPort(ID::Y);
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auto &sig_a = cell->getPort(ID::A);
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auto &sig_b = cell->getPort(ID::B);
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auto sig_s = cell->getPort(ID::S);
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if (cell->type == ID($mux))
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sig_s = SigSpec(sig_s[0], GetSize(sig_y));
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forward_tags(sig_y, sig_a);
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forward_tags(sig_y, sig_b);
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forward_tags(sig_y, sig_s);
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return;
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}
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if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
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FfData ff(&initvals, cell);
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if (ff.has_clk || ff.has_gclk)
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forward_tags(ff.sig_q, ff.sig_d);
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return;
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}
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// Single output but, sensitive to all inputs
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if (cell->type.in(
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ID($le), ID($lt), ID($ge), ID($gt),
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ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor),
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ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
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ID($eq), ID($ne)
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)) {
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auto &sig_y = cell->getPort(ID::Y);
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add_tags(sig_y[0], tags(cell));
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return;
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}
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// Fallback, propagate tags from all inputs to all outputs
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add_tags(cell, tags(cell));
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if (cell->type.in(
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ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_),
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ID($_XOR_), ID($_XNOR_), ID($_NOT_), ID($_BUF_), ID($_MUX_),
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ID($assert), ID($assume)
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)) {
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return;
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}
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// This isn't a correctness concern (unless cell is a module generating
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// tags), but we may end up generating a lot of extra logic when
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// reaching this
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if (!warned_cells.insert(cell).second)
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return;
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if (cell->type.isPublic())
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log_warning("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type));
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else
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log_debug("Unhandled cell %s (%s) during tag propagation\n", log_id(cell), log_id(cell->type));
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}
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void process_cell(IdString tag, Cell *cell)
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{
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if (cell->type == ID($set_tag)) {
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IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
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auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A));
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auto &sig_y = cell->getPort(ID::Y);
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if (cell_tag == tag) {
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auto &sig_set = cell->getPort(ID::SET);
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auto &sig_clr = cell->getPort(ID::CLR);
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tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr));
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tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set);
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}
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emit_tag_signal(tag, sig_y, tag_sig_a);
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return;
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}
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if (cell->type == ID($get_tag)) {
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log_assert(false);
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}
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if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) {
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auto &sig_y = cell->getPort(ID::Y);
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auto sig_a = cell->getPort(ID::A);
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if (cell->type.in(ID($not), ID($or))) {
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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}
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emit_tag_signal(tag, sig_y, tag_signal(tag, sig_a));
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return;
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}
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if (cell->type.in(
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ID($and), ID($or),
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ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_)
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)) {
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auto &sig_y = cell->getPort(ID::Y);
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auto sig_a = cell->getPort(ID::A);
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auto sig_b = cell->getPort(ID::B);
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if (cell->type.in(ID($and), ID($or))) {
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
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}
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bool inv_a = false;
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bool inv_b = false;
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|
||||
if (cell->type.in(ID($or), ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
|
||||
inv_a ^= true, inv_b ^= true;
|
||||
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
|
||||
inv_b ^= true;
|
||||
|
||||
if (inv_a)
|
||||
sig_a = autoNot(NEW_ID, sig_a);
|
||||
if (inv_b)
|
||||
sig_b = autoNot(NEW_ID, sig_b);
|
||||
|
||||
auto group_sig_a = tag_group_signal(tag, sig_a);
|
||||
auto group_sig_b = tag_group_signal(tag, sig_b);
|
||||
|
||||
auto tag_sig_a = tag_signal(tag, sig_a);
|
||||
auto tag_sig_b = tag_signal(tag, sig_b);
|
||||
|
||||
|
||||
// Does this input allow propagating (doesn't fix output or same tag group)
|
||||
sig_a = autoOr(NEW_ID, sig_a, group_sig_a);
|
||||
sig_b = autoOr(NEW_ID, sig_b, group_sig_b);
|
||||
|
||||
// Mask input tags by whether the other side allows propagation
|
||||
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, sig_b);
|
||||
tag_sig_b = autoAnd(NEW_ID, tag_sig_b, sig_a);
|
||||
|
||||
|
||||
auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b);
|
||||
emit_tag_signal(tag, sig_y, tag_sig);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) {
|
||||
auto &sig_y = cell->getPort(ID::Y);
|
||||
auto sig_a = cell->getPort(ID::A);
|
||||
auto sig_b = cell->getPort(ID::B);
|
||||
if (cell->type.in(ID($xor), ID($xnor))) {
|
||||
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
|
||||
}
|
||||
|
||||
auto tag_sig_a = tag_signal(tag, sig_a);
|
||||
auto tag_sig_b = tag_signal(tag, sig_b);
|
||||
|
||||
auto tag_sig = autoOr(NEW_ID, tag_sig_a, tag_sig_b);
|
||||
emit_tag_signal(tag, sig_y, tag_sig);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
|
||||
auto &sig_y = cell->getPort(ID::Y);
|
||||
auto &sig_a = cell->getPort(ID::A);
|
||||
auto &sig_b = cell->getPort(ID::B);
|
||||
auto sig_s = cell->getPort(ID::S);
|
||||
|
||||
if (cell->type == ID($mux))
|
||||
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
|
||||
|
||||
auto group_sig_a = tag_group_signal(tag, sig_a);
|
||||
auto group_sig_b = tag_group_signal(tag, sig_b);
|
||||
auto group_sig_s = tag_group_signal(tag, sig_s);
|
||||
|
||||
auto prop_s = autoOr(NEW_ID,
|
||||
autoXor(NEW_ID, sig_a, sig_b),
|
||||
autoOr(NEW_ID, group_sig_a, group_sig_b));
|
||||
|
||||
auto prop_a = autoOr(NEW_ID, autoNot(NEW_ID, sig_s), group_sig_s);
|
||||
auto prop_b = autoOr(NEW_ID, sig_s, group_sig_s);
|
||||
|
||||
auto tag_sig_a = tag_signal(tag, sig_a);
|
||||
auto tag_sig_b = tag_signal(tag, sig_b);
|
||||
auto tag_sig_s = tag_signal(tag, sig_s);
|
||||
|
||||
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, prop_a);
|
||||
tag_sig_b = autoAnd(NEW_ID, tag_sig_b, prop_b);
|
||||
tag_sig_s = autoAnd(NEW_ID, tag_sig_s, prop_s);
|
||||
|
||||
auto tag_sig = autoOr(NEW_ID, tag_sig_s,
|
||||
autoOr(NEW_ID, tag_sig_a, tag_sig_b));
|
||||
emit_tag_signal(tag, sig_y, tag_sig);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) {
|
||||
auto &sig_y = cell->getPort(ID::Y);
|
||||
auto sig_a = cell->getPort(ID::A);
|
||||
auto sig_b = cell->getPort(ID::B);
|
||||
int width = std::max(GetSize(sig_a), GetSize(sig_b));
|
||||
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
|
||||
|
||||
auto group_sig_a = tag_group_signal(tag, sig_a);
|
||||
auto group_sig_b = tag_group_signal(tag, sig_b);
|
||||
|
||||
auto tag_sig_a = tag_signal(tag, sig_a);
|
||||
auto tag_sig_b = tag_signal(tag, sig_b);
|
||||
|
||||
auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b);
|
||||
// The output can only be affected by the tagged inputs if all group-untagged bits are equal
|
||||
|
||||
auto masked_a = autoOr(NEW_ID, sig_a, group_sig);
|
||||
auto masked_b = autoOr(NEW_ID, sig_b, group_sig);
|
||||
|
||||
auto prop = autoEq(NEW_ID, masked_a, masked_b);
|
||||
|
||||
auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b}));
|
||||
tag_sig.extend_u0(GetSize(sig_y), false);
|
||||
emit_tag_signal(tag, sig_y, tag_sig);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) {
|
||||
auto &sig_y = cell->getPort(ID::Y);
|
||||
auto sig_a = cell->getPort(ID::A);
|
||||
auto sig_b = cell->getPort(ID::B);
|
||||
int width = std::max(GetSize(sig_a), GetSize(sig_b));
|
||||
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
|
||||
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
|
||||
|
||||
if (cell->type.in(ID($gt), ID($le)))
|
||||
std::swap(sig_a, sig_b);
|
||||
|
||||
auto group_sig_a = tag_group_signal(tag, sig_a);
|
||||
auto group_sig_b = tag_group_signal(tag, sig_b);
|
||||
|
||||
auto tag_sig_a = tag_signal(tag, sig_a);
|
||||
auto tag_sig_b = tag_signal(tag, sig_b);
|
||||
|
||||
auto group_sig = autoOr(NEW_ID, group_sig_a, group_sig_b);
|
||||
// The output can only be affected by the tagged inputs if the greatest possible sig_a is
|
||||
// greater or equal to the least possible sig_b
|
||||
auto masked_a = autoOr(NEW_ID, sig_a, group_sig);
|
||||
auto masked_b = autoAnd(NEW_ID, sig_b, autoNot(NEW_ID, group_sig));
|
||||
|
||||
auto prop = autoGe(NEW_ID, masked_a, masked_b);
|
||||
|
||||
auto tag_sig = autoAnd(NEW_ID, prop, autoReduceOr(NEW_ID, {tag_sig_a, tag_sig_b}));
|
||||
tag_sig.extend_u0(GetSize(sig_y), false);
|
||||
emit_tag_signal(tag, sig_y, tag_sig);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
|
||||
auto &sig_y = cell->getPort(ID::Y);
|
||||
auto sig_a = cell->getPort(ID::A);
|
||||
|
||||
if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
|
||||
sig_a = autoNot(NEW_ID, sig_a);
|
||||
|
||||
auto group_sig_a = tag_group_signal(tag, sig_a);
|
||||
auto tag_sig_a = tag_signal(tag, sig_a);
|
||||
|
||||
auto filled = autoOr(NEW_ID, sig_a, group_sig_a);
|
||||
|
||||
auto prop = autoReduceAnd(NEW_ID, filled);
|
||||
auto tagged = autoReduceOr(NEW_ID, tag_sig_a);
|
||||
auto tag_sig = autoAnd(NEW_ID, prop, tagged);
|
||||
tag_sig.extend_u0(GetSize(sig_y), false);
|
||||
emit_tag_signal(tag, sig_y, tag_sig);
|
||||
return;
|
||||
}
|
||||
|
||||
if (RTLIL::builtin_ff_cell_types().count(cell->type) || cell->type == ID($anyinit)) {
|
||||
FfData ff(&initvals, cell);
|
||||
// TODO handle some more variants
|
||||
if ((ff.has_clk || ff.has_gclk) && !ff.has_ce && !ff.has_aload && !ff.has_srst && !ff.has_arst && !ff.has_sr) {
|
||||
if (ff.has_clk && !tags(ff.sig_clk).empty())
|
||||
log_warning("Tags on CLK input ignored for %s (%s)\n", log_id(cell), log_id(cell->type));
|
||||
|
||||
int width = ff.width;
|
||||
|
||||
auto sig_q = ff.sig_q;
|
||||
auto sig_d = ff.sig_d;
|
||||
|
||||
ff.name = NEW_ID;
|
||||
ff.cell = nullptr;
|
||||
ff.sig_d = tag_signal(tag, ff.sig_d);
|
||||
ff.sig_q = module->addWire(NEW_ID, width);
|
||||
ff.is_anyinit = false;
|
||||
ff.val_init = Const(0, width);
|
||||
ff.emit();
|
||||
|
||||
emit_tag_signal(tag, sig_q, ff.sig_q);
|
||||
return;
|
||||
} else {
|
||||
log_warning("Unhandled FF-cell %s (%s), consider running clk2fflogic, async2sync and/or dffunmap\n", log_id(cell), log_id(cell->type));
|
||||
|
||||
// For unhandled FFs, the default propagation would cause combinational loops
|
||||
emit_tag_signal(tag, ff.sig_q, Const(0, ff.width));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// Fallback
|
||||
SigSpec tag_input;
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (cell->input(conn.first)) {
|
||||
auto tag_sig = tag_signal(tag, conn.second);
|
||||
tag_input.append(tag_sig);
|
||||
}
|
||||
}
|
||||
|
||||
SigBit any_tagged = autoReduceOr(NEW_ID, tag_input);
|
||||
|
||||
for (auto &conn : cell->connections()) {
|
||||
if (cell->output(conn.first)) {
|
||||
emit_tag_signal(tag, conn.second, SigSpec(any_tagged, GetSize(conn.second)));
|
||||
}
|
||||
}
|
||||
|
||||
// As fallback we propagate all tags from all inputs to all outputs,
|
||||
// which is an over-approximation (unless the cell is a module that
|
||||
// generates tags itself in which case it could be arbitrary).
|
||||
if (warned_cells.insert(cell).second)
|
||||
log_warning("Unhandled cell %s (%s) while emitting tag signals\n", log_id(cell), log_id(cell->type));
|
||||
}
|
||||
|
||||
void emit_tags()
|
||||
{
|
||||
warned_cells.clear();
|
||||
std::vector<Cell *> get_tag_cells;
|
||||
for (auto cell : module->selected_cells())
|
||||
if (cell->type == ID($get_tag))
|
||||
get_tag_cells.push_back(cell);
|
||||
|
||||
for (auto cell : get_tag_cells) {
|
||||
auto &sig_a = cell->getPort(ID::A);
|
||||
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
|
||||
|
||||
tag_signal(tag, sig_a);
|
||||
}
|
||||
|
||||
if (options.tag_public)
|
||||
{
|
||||
std::vector<Wire *> public_wires;
|
||||
|
||||
for (auto wire : module->selected_wires())
|
||||
if (wire->name.isPublic())
|
||||
public_wires.push_back(wire);
|
||||
|
||||
for (auto wire : public_wires) {
|
||||
for (auto tag : tag_pool(tags(SigSpec(wire)))) {
|
||||
auto tag_sig = tag_signal(tag, SigSpec(wire));
|
||||
if (tag_sig.is_fully_zero())
|
||||
continue;
|
||||
|
||||
int index = 0;
|
||||
auto name = module->uniquify(stringf("%s:%s", wire->name.c_str(), tag.c_str() + 1), index);
|
||||
auto hdlname = wire->get_hdlname_attribute();
|
||||
|
||||
if (!hdlname.empty())
|
||||
hdlname.back() += index ?
|
||||
stringf(":%s_%d", tag.c_str() + 1, index) :
|
||||
stringf(":%s", tag.c_str() + 1);
|
||||
|
||||
auto tag_wire = module->addWire(name, wire->width);
|
||||
|
||||
tag_wire->set_bool_attribute(ID::keep);
|
||||
tag_wire->set_bool_attribute(ID(dft_tag));
|
||||
if (!hdlname.empty())
|
||||
tag_wire->set_hdlname_attribute(hdlname);
|
||||
|
||||
module->connect(tag_wire, tag_sig);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void replace_dft_cells()
|
||||
{
|
||||
std::vector<Cell *> get_tag_cells;
|
||||
std::vector<Cell *> set_tag_cells;
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type == ID($get_tag))
|
||||
get_tag_cells.push_back(cell);
|
||||
|
||||
if (cell->type == ID($set_tag))
|
||||
set_tag_cells.push_back(cell);
|
||||
|
||||
if (cell->type.in(ID($overwrite_tag), ID($original_tag)))
|
||||
log_error("$overwrite_tag and $original_tag are not supported yet\n");
|
||||
// TODO these have to be rewritten as early as possible, so it should be a separate pass invocation
|
||||
}
|
||||
|
||||
for (auto cell : set_tag_cells) {
|
||||
auto &sig_a = cell->getPort(ID::A);
|
||||
auto &sig_y = cell->getPort(ID::Y);
|
||||
module->connect(sig_y, sig_a);
|
||||
module->remove(cell);
|
||||
}
|
||||
|
||||
for (auto cell : get_tag_cells) {
|
||||
auto &sig_a = cell->getPort(ID::A);
|
||||
auto &sig_y = cell->getPort(ID::Y);
|
||||
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string().c_str());
|
||||
|
||||
auto tag_sig = tag_signal(tag, sig_a);
|
||||
module->connect(sig_y, tag_sig);
|
||||
module->remove(cell);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
SigSpec autoAnd(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
|
||||
{
|
||||
log_assert(GetSize(sig_a) == GetSize(sig_b));
|
||||
if (sig_a.is_fully_zero() || sig_b.is_fully_ones() || sig_a == sig_b)
|
||||
return sig_a;
|
||||
if (sig_a.is_fully_ones() || sig_b.is_fully_zero())
|
||||
return sig_b;
|
||||
|
||||
return module->And(name, sig_a, sig_b);
|
||||
}
|
||||
|
||||
SigSpec autoOr(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
|
||||
{
|
||||
log_assert(GetSize(sig_a) == GetSize(sig_b));
|
||||
if (sig_a.is_fully_ones() || sig_b.is_fully_zero() || sig_a == sig_b)
|
||||
return sig_a;
|
||||
if (sig_a.is_fully_zero() || sig_b.is_fully_ones())
|
||||
return sig_b;
|
||||
|
||||
return module->Or(name, sig_a, sig_b);
|
||||
}
|
||||
|
||||
SigSpec autoXor(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
|
||||
{
|
||||
log_assert(GetSize(sig_a) == GetSize(sig_b));
|
||||
if (sig_a == sig_b)
|
||||
return Const(State::S0, GetSize(sig_a));
|
||||
if (sig_a.is_fully_zero())
|
||||
return sig_b;
|
||||
if (sig_b.is_fully_zero())
|
||||
return sig_a;
|
||||
if (sig_a.is_fully_ones())
|
||||
return autoNot(name, sig_b);
|
||||
if (sig_b.is_fully_ones())
|
||||
return autoNot(name, sig_a);
|
||||
return module->Xor(name, sig_a, sig_b);
|
||||
}
|
||||
|
||||
SigSpec autoXnor(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
|
||||
{
|
||||
log_assert(GetSize(sig_a) == GetSize(sig_b));
|
||||
if (sig_a == sig_b)
|
||||
return Const(State::S1, GetSize(sig_a));
|
||||
if (sig_a.is_fully_ones())
|
||||
return sig_b;
|
||||
if (sig_b.is_fully_ones())
|
||||
return sig_a;
|
||||
if (sig_a.is_fully_zero())
|
||||
return autoNot(name, sig_b);
|
||||
if (sig_b.is_fully_zero())
|
||||
return autoNot(name, sig_a);
|
||||
return module->Xnor(name, sig_a, sig_b);
|
||||
}
|
||||
|
||||
SigSpec autoNot(IdString name, const SigSpec &sig_a)
|
||||
{
|
||||
if (sig_a.is_fully_const()) {
|
||||
auto const_val = sig_a.as_const();
|
||||
for (auto &bit : const_val.bits)
|
||||
bit = bit == State::S0 ? State::S1 : bit == State::S1 ? State::S0 : bit;
|
||||
return const_val;
|
||||
}
|
||||
return module->Not(name, sig_a);
|
||||
}
|
||||
|
||||
SigSpec autoEq(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
|
||||
{
|
||||
log_assert(GetSize(sig_a) == GetSize(sig_b));
|
||||
if (sig_a == sig_b)
|
||||
return State::S1;
|
||||
for (int i = 0; i < GetSize(sig_a); i++) {
|
||||
auto bit_a = sig_a[i];
|
||||
auto bit_b = sig_b[i];
|
||||
if (bit_a.is_wire() || bit_b.is_wire())
|
||||
continue;
|
||||
if ((bit_a.data == State::S0 && bit_b.data == State::S1) ||
|
||||
(bit_a.data == State::S1 && bit_b.data == State::S0))
|
||||
return State::S0;
|
||||
}
|
||||
|
||||
return module->Eq(name, sig_a, sig_b);
|
||||
}
|
||||
|
||||
SigSpec autoGe(IdString name, const SigSpec &sig_a, const SigSpec &sig_b)
|
||||
{
|
||||
log_assert(GetSize(sig_a) == GetSize(sig_b));
|
||||
if (sig_a == sig_b || sig_a.is_fully_ones())
|
||||
return State::S1;
|
||||
if (sig_b.is_fully_zero())
|
||||
return State::S1;
|
||||
|
||||
return module->Ge(name, sig_a, sig_b);
|
||||
}
|
||||
|
||||
SigSpec autoReduceAnd(IdString name, const SigSpec &sig_a)
|
||||
{
|
||||
if (GetSize(sig_a) == 0)
|
||||
return State::S1;
|
||||
|
||||
if (GetSize(sig_a) == 1 || sig_a == SigSpec(sig_a[0], GetSize(sig_a)))
|
||||
return sig_a[0];
|
||||
for (auto bit : sig_a)
|
||||
if (!bit.is_wire() && bit.data == State::S0)
|
||||
return State::S0;
|
||||
if (sig_a.is_fully_ones())
|
||||
return State::S1;
|
||||
return module->ReduceAnd(name, sig_a);
|
||||
}
|
||||
|
||||
SigSpec autoReduceOr(IdString name, const SigSpec &sig_a)
|
||||
{
|
||||
if (GetSize(sig_a) == 0)
|
||||
return State::S0;
|
||||
|
||||
if (GetSize(sig_a) == 1 || sig_a == SigSpec(sig_a[0], GetSize(sig_a)))
|
||||
return sig_a[0];
|
||||
for (auto bit : sig_a)
|
||||
if (!bit.is_wire() && bit.data == State::S1)
|
||||
return State::S1;
|
||||
if (sig_a.is_fully_zero())
|
||||
return State::S0;
|
||||
return module->ReduceOr(name, sig_a);
|
||||
}
|
||||
};
|
||||
|
||||
struct DftTagPass : public Pass {
|
||||
DftTagPass() : Pass("dft_tag", "create tagging logic for data flow tracking") {}
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" dft_tag [options] [selection]\n");
|
||||
log("\n");
|
||||
log("This pass... TODO\n");
|
||||
log("\n");
|
||||
log(" -tag-public\n");
|
||||
log(" For each public wire that may carry tagged data, create a new public\n");
|
||||
log(" wire (named <wirename>:<tagname>) that carries the tag bits. Note\n");
|
||||
log(" that without this, tagging logic will only be emitted as required\n");
|
||||
log(" for uses of $get_tag.\n");
|
||||
log("\n");
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
DftTagOptions options;
|
||||
|
||||
log_header(design, "Executing DFT_TAG pass.\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
if (args[argidx] == "-tag-public") {
|
||||
options.tag_public = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
DftTagWorker worker(module, options);
|
||||
|
||||
log_debug("Propagate tagged signals.\n");
|
||||
worker.propagate_tags();
|
||||
|
||||
log_debug("Emit tag signals and logic.\n");
|
||||
worker.emit_tags();
|
||||
|
||||
log_debug("Replace dft cells.\n");
|
||||
worker.replace_dft_cells();
|
||||
}
|
||||
}
|
||||
} DftTagPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
Loading…
Reference in a new issue