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Code Activity
14518 commits 99 branches 53 tags 46 MiB
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1368 commits

Author SHA1 Message Date
Martin Povišer
2a3f60bc06 abc_new: Support abc9_box mode on ordinary design hierarchy 
Previously the `abc9_box` mode was reserved to modules with the
`blackbox` or `whitebox` attribute. Allow `abc9_box` on ordinary modules
when doing hierarchical synthesis.
 2024-12-10 14:27:29 +01:00
Martin Povišer
285f24d764 abc_new: Support per-module script override 2024-12-10 14:27:29 +01:00
Martin Povišer
14ee5ce800
Merge pull request #4787 from povik/booth-macc 
booth: Map simple `$macc` instances too
 2024-12-04 11:49:34 +01:00
Emil J
3b8e8ee012
Merge pull request #4797 from YosysHQ/emil/multiple-liberty 
Allow multiple -liberty args in dfflibmap and clockgate
 2024-12-04 11:18:52 +01:00
Martin Povišer
384c191192
Merge pull request #4775 from povik/dont_map 
techmap: Add `-dont_map` for selective disabling of rules
 2024-12-03 20:21:47 +01:00
Martin Povišer
1c7bb700c9 techmap: Rephrase help 2024-12-03 20:20:00 +01:00
Emil J. Tywoniak
6edf9c86cb libparse: add LibertyMergedCells, enable multiple -liberty args for dfflibmap and clockgate 2024-12-03 17:36:00 +01:00
Emil J. Tywoniak
60fb241cb3 clockgate: clean up argument parsing 2024-12-03 17:35:10 +01:00
KrystalDelusion
889894a6d2
Merge pull request #4790 from YosysHQ/emil/clockgate-warnings 
clockgate: reduce build warnings
 2024-12-03 13:25:52 +13:00
Lofty
fd05f73d50 dfflibmap: demote some warnings to debug 2024-12-02 14:17:51 +00:00
Emil J. Tywoniak
6b006e5f61 clockgate: reduce build warnings 2024-12-02 10:07:01 +01:00
Martin Povišer
1ded817beb booth: Map simple $macc instances too 2024-12-01 16:00:04 +01:00
Martin Povišer
2962f8fa88 techmap: Add -dont_map for selective disabling of rules 2024-11-27 15:54:37 +01:00
Emil J. Tywoniak
4d96cbec75 clockgate: reduce errors to warnings 2024-11-18 18:32:18 +01:00
Emil J. Tywoniak
983c54c75f clockgate: help string add -dont_use and -liberty 2024-11-18 13:57:49 +01:00
Emil J. Tywoniak
a5bc36f77e clockgate: add -dont_use 2024-11-18 13:45:30 +01:00
Emil J. Tywoniak
e6793da9a0 clockgate: refactor 2024-11-18 12:50:25 +01:00
Emil J. Tywoniak
45880ea7f2 clockgate: add -liberty 2024-11-14 20:37:59 +01:00
Lofty
4f40187759 dfflibmap: move expression code into libparse 2024-11-13 16:06:57 +00:00
Lofty
08ed2c765e dfflibmap: enable inference 2024-11-13 15:57:45 +00:00
Martin Povišer
9da7341003
Merge pull request #4727 from georgerennie/george/bufnorm_constants2 
bufnorm: preserve constant bits when mapping back to connections
 2024-11-13 14:32:15 +01:00
Emil J. Tywoniak
49e1597ea4 filterlib: preserve value quotes 2024-11-12 01:21:07 +01:00
George Rennie
ff6c9446c0 bufnorm: preserve constant bits when mapping back to connections 2024-11-12 01:05:15 +01:00
George Rennie
8f6058a7d6 bufnorm: preserve constant bits driving wires 2024-11-07 11:48:48 +01:00
Martin Povišer
cbe73c9047 cellmatch: Visit whiteboxes for -derive_luts 2024-11-04 14:28:46 +01:00
Martin Povišer
c9ed6d8dcf cellmatch: Rename -lut_attrs to -derive_luts; document option 2024-11-04 14:28:40 +01:00
Emil J. Tywoniak
785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Martin Povišer
a00137c2f6
Merge pull request #4625 from povik/cellmatch-lut 
cellmatch: Size the `lut` attribute
 2024-10-11 14:08:55 +02:00
Martin Povišer
9479d3bd3c
Merge pull request #4637 from YosysHQ/emil/bufnorm-warning 
bufnorm: avoid warning. NFC
 2024-10-07 18:01:42 +02:00
Emil J. Tywoniak
a76bcdc58f bufnorm: avoid remove warning. NFC 2024-10-07 17:58:48 +02:00
Martin Povišer
2e587c835f abc9_exe: Document SC mapping options 2024-10-07 12:03:49 +02:00
Martin Povišer
3b6dcc7bd0 abc9_exe: Remove -genlib option 2024-10-07 12:03:49 +02:00
Martin Povišer
e0a86d5483 abc_new: Start new command for aiger2-based round trip 2024-10-07 12:03:49 +02:00
Martin Povišer
e58a9b6ab6 abc9: Understand ASIC options similar to abc 2024-10-07 12:03:48 +02:00
Martin Povišer
ec42b42bd9 cellmatch: Size the lut attribute 2024-10-02 11:29:54 +02:00
Martin Povišer
38de01807e Mark bufnorm experimental 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
80119386c0 Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
8bb70bac8d Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
d027ead4b5 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
f4b7ea5fb3 Improvements in "bufnorm" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
32808a0393 Improvements and fixes to "bufnorm" cmd 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
d0b5dfa6ef Add bufnorm pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2024-09-17 10:46:20 +02:00
Emil J. Tywoniak
f193bcf683 clockgate: help string 2024-09-16 14:20:33 +02:00
Emil J. Tywoniak
be7c93ec6d clockgate: 1-bit const 0 2024-09-16 13:58:27 +02:00
Emil J
a8a92d3469
clockgate: help string 
Co-authored-by: Martin Povišer <povik@cutebit.org>
 2024-09-16 13:55:53 +02:00
Emil J. Tywoniak
1e999a3cb7 clockgate: EN can be a bit on a multi-bit wire 2024-09-11 19:18:25 +02:00
Emil J. Tywoniak
8b464341c2 clockgate: no initvals 2024-09-11 10:24:48 +02:00
Emil J. Tywoniak
7e473299bd clockgate: bail on constant signals 2024-09-09 21:20:19 +02:00
Emil J. Tywoniak
e64fceef70 clockgate: prototype clock gating 2024-09-09 15:00:54 +02:00
Krystine Sherwin
7b47f645d7
Address warnings 
- Setting default values
- Fixing mismatched types
- Guarding unused var
 2024-08-16 04:30:31 +12:00