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Author SHA1 Message Date
Matt Johnston
2a3804139f opt_mem_merge: Combine memories for byte enable. 
The RAMs inferred by GHDL are split into separate instances
for byte enables. This pass recombines memories that have the same
input address (and matching characteristics) allowing a single
BRAM to be used with byte enables.

Work in progress, needs more checks for memory compatibility
Briefly tested to work for microwatt
 2022-01-14 14:40:04 +08:00
github-actions[bot]
61324cf55f Bump version 2022-01-12 00:59:23 +00:00
Miodrag Milanovic
b91533d9f2 Forgot one 2022-01-11 09:39:45 +01:00
Miodrag Milanovic
883b4fb7e6 Change url to https 2022-01-11 08:56:33 +01:00
Miodrag Milanovic
c428a894c0 Next dev cycle 2022-01-11 08:39:34 +01:00
Miodrag Milanovic
8b1eafc3ad Release version 0.13 2022-01-11 08:35:50 +01:00
Miodrag Milanovic
64972360a8 Update CHANGELOG 2022-01-11 08:21:12 +01:00
github-actions[bot]
0feba821a8 Bump version 2022-01-09 01:01:33 +00:00
Zachary Snow
aa35f24290 sv: auto add nosync to certain always_comb local vars 
If a local variable is always assigned before it is used, then adding
nosync prevents latches from being needlessly generated.
 2022-01-07 22:53:22 -07:00
Zachary Snow
828e85068f sv: fix size cast internal expression extension 2022-01-07 21:21:02 -07:00
github-actions[bot]
59a7150344 Bump version 2022-01-05 01:00:24 +00:00
Zachary Snow
66447e8faf logger: fix unmatched expected warnings and errors 
- Prevent unmatched expected error patterns from self-matching
- Prevent infinite recursion on unmatched expected warnings
- Always print the error message for unmatched error patterns
- Add test coverage for all unmatched message types
- Add test coverage for excess matched logs and warnings
 2022-01-04 13:39:34 -07:00
Austin Seipp
b022fe61a7 opt_dff: fix sequence point copy paste bug 
Newer GCCs emit the following warning for opt_dff:

    passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point]
      560 |      ff.has_clk = ff.has_ce = ff.has_clk = false;
          |      ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Which is correct: the order of whether the read or write of has_clk
occurs first is undefined since there is no sequence point between them.

This is almost certainly just a typo/copy paste error and objectively
wrong, so just fix it.

Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2022-01-04 18:18:08 +01:00
gatecat
493b5e03e7 manual: Fix cell-stmt order 
Signed-off-by: gatecat <gatecat@ds0.me>
 2022-01-03 18:17:10 -07:00
github-actions[bot]
361916ad3e Bump version 2022-01-04 00:58:28 +00:00
Zachary Snow
e0e4dfb55e fix iverilog compatibility for new case expr tests 2022-01-03 12:11:41 -07:00
Zachary Snow
207af4196b fixup verilog doubleslash test 
- add generated doubleslash.v to .gitignore
- ensure backend verilog can be read again
 2022-01-03 08:17:46 -07:00
Zachary Snow
8c509a5659 sv: fix size cast clipping expression width 2022-01-03 08:17:35 -07:00
Miodrag Milanovic
cb17eeaf50 Update manual 2022-01-03 11:57:11 +01:00
github-actions[bot]
cfe940a98b Bump version 2021-12-26 01:00:33 +00:00
Catherine
ebe396a2ab
Merge pull request #3127 from whitequark/cxxrtl-no-reset-elided 
cxxrtl: don't reset elided wires with \init attribute
 2021-12-25 12:29:44 +00:00
Catherine
fc049e84a9 cxxrtl: don't reset elided wires with \init attribute. 2021-12-25 01:06:10 +00:00
github-actions[bot]
7407a7f3ef Bump version 2021-12-22 00:58:25 +00:00
Lofty
d015c2b48a intel_alm: disable 256x40 M10K mode 
This BRAM mode uses both address ports, making it effectively single-port.
Since memory_bram can't presently map to single-port memories, remove it.
 2021-12-22 00:42:33 +01:00
github-actions[bot]
229980d663 Bump version 2021-12-21 00:59:45 +00:00
Marcelina Kościelnicka
f84c9d8e17 memory_share: Fix SAT-based sharing for wide ports. 
Fixes #3117.
 2021-12-20 18:40:14 +01:00
github-actions[bot]
f599c148c5 Bump version 2021-12-19 01:00:40 +00:00
Zachary Snow
7608985d2c fix width detection of array querying function in case and case item expressions 
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
 2021-12-17 21:22:08 -07:00
github-actions[bot]
60c3ea367c Bump version 2021-12-17 00:58:02 +00:00
Catherine
ed4642e18e
Merge pull request #3115 from whitequark/issue-3112 
cxxrtl: demote wires not inlinable only in debug_eval to locals
 2021-12-16 07:29:29 +00:00
Catherine
73eea51613
Merge pull request #3114 from whitequark/issue-3113 
bugpoint: avoid infinite loop between -connections and -wires
 2021-12-16 07:29:19 +00:00
Thomas Sailer
4cd2f03e36 preprocessor: do not destroy double slash escaped identifiers 
The preprocessor currently destroys double slash containing escaped
identifiers (for example \a//b ). This is due to next_token trying to
convert single line comments (//) into /* */ comments. This then leads
to an unintuitive error message like this:
ERROR: syntax error, unexpected '*'

This patch fixes the error by recognizing escaped identifiers and
returning them as single token. It also adds a testcase.
 2021-12-15 18:06:02 -07:00
Catherine
7f2ea7d222 cxxrtl: demote wires not inlinable only in debug_eval to locals. 
Fixes #3112.

Co-authored-by: Irides <irides@irides.network>
 2021-12-15 09:14:33 +00:00
Catherine
4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires. 
Fixes #3113.
 2021-12-15 08:17:02 +00:00
github-actions[bot]
477eeefd9b Bump version 2021-12-15 00:59:04 +00:00
Catherine
5dadcc85b7
Merge pull request #3111 from whitequark/issue-3110 
Fix null pointer dereference after failing to extract DFF from memory
 2021-12-14 21:25:06 +00:00
Claire Xenia Wolf
e1c7a9a647 Hotfix for run_shell auto-detection 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-14 21:38:58 +01:00
Catherine
48ed6d998b Fix null pointer dereference after failing to extract DFF from memory. 
Fixes #3110.
 2021-12-14 16:27:37 +00:00
github-actions[bot]
b07ca8756a Bump version 2021-12-14 00:59:10 +00:00
Claire Xen
5e5c8a54ce
Merge pull request #3108 from YosysHQ/claire/verificdefs 
Add YOSYS to the implicitly defined verilog macros in verific
 2021-12-13 22:03:29 +01:00
Claire Xenia Wolf
313340aed5 Add YOSYS to the implicitly defined verilog macros in verific 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-13 18:20:08 +01:00
github-actions[bot]
19a38222e7 Bump version 2021-12-13 00:55:45 +00:00
Marcelina Kościelnicka
0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Catherine
bdc6ba019c
Merge pull request #3105 from whitequark/cxxrtl-reset-memories-2 
cxxrtl: preserve interior memory pointers across reset
 2021-12-12 01:23:03 +00:00
github-actions[bot]
6a7253b46e Bump version 2021-12-12 01:12:53 +00:00
Marcelina Kościelnicka
26f0f6bb0b Fix unused param warning with ENABLE_NDEBUG. 2021-12-12 01:22:28 +01:00
Marcelina Kościelnicka
d019b4e681 rtlil: Dump empty connections when whole module is selected. 
Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing.
 2021-12-12 01:22:06 +01:00
Catherine
55c9fb3b18 cxxrtl: preserve interior memory pointers across reset. 
Before this commit, values, wires, and memories with an initializer
were value-initialized in emitted C++ code. After this commit, all
values, wires, and memories are default-initialized, and the default
constructor of generated modules calls the reset() method, which
assigns the members that have an initializer.
 2021-12-11 16:40:06 +00:00
Catherine
21fbdb6638
Merge pull request #3103 from whitequark/write_verilog-more-zero-width-values 
write_verilog: dump zero width sigspecs correctly
 2021-12-11 16:24:47 +00:00
whitequark
7c9e498662 cxxrtl: use unique_ptr<value<>[]> to store memory contents. 
This makes the depth properly immutable.
 2021-12-11 14:52:37 +00:00