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Author SHA1 Message Date
whitequark
8b44198e23 flowmap: construct a max-volume max-flow min-cut, not just any one. 2019-01-06 19:51:37 +00:00
Clifford Wolf
a2c51d50fb
Merge pull request #780 from phire/rename_from_wire 
Rename cells based on the wires they drive.
 2019-01-06 11:35:31 +01:00
Scott Mansell
62c90c4e17 Rename cells based on the wires they drive. 2019-01-06 19:00:16 +13:00
Clifford Wolf
f589ce86ba Add skeleton Yosys-Libero igloo2 example project 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 17:02:01 +01:00
Clifford Wolf
17ceab92a9 Bugfix in Verilog string handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-05 12:10:24 +01:00
whitequark
2fcc1ee72e flowmap: add -minlut option, to allow postprocessing with opt_lut. 2019-01-04 21:18:03 +00:00
Clifford Wolf
e041ae3c6d
Merge pull request #777 from mmicko/achronix_cell_sim_fix 
Fix cells_sim.v for Achronix FPGA
 2019-01-04 15:18:18 +01:00
Miodrag Milanovic
50ef4561d4 Fix cells_sim.v for Achronix FPGA 2019-01-04 15:15:23 +01:00
Clifford Wolf
6d1e7e9403 Remove -m32 Verific eval lib build instructions 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-04 15:03:49 +01:00
Clifford Wolf
7a2db03aa7
Merge pull request #776 from mmicko/unify_noflatten 
Unify usage of noflatten among architectures
 2019-01-04 14:56:04 +01:00
Clifford Wolf
f5d23d4c7a Update Verific default path 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-04 14:44:35 +01:00
whitequark
9bc5cf0844 flowmap: cleanup for clarity. NFCI. 2019-01-04 13:04:20 +00:00
Miodrag Milanovic
3b17c9018a Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
whitequark
fd21564deb flowmap: improve debug graph output. NFC. 2019-01-04 03:30:04 +00:00
whitequark
7850a0c28a flowmap: add link to longer version of paper. NFC. 2019-01-04 02:33:10 +00:00
Clifford Wolf
d98fe8ce1f
Merge pull request #775 from whitequark/opt_flowmap 
flowmap: new techmap pass
 2019-01-03 17:03:18 +01:00
whitequark
07af772a72 flowmap: new techmap pass. 2019-01-03 14:28:19 +00:00
Clifford Wolf
0fc6e2bfcf
Merge pull request #770 from whitequark/opt_expr_cmp 
opt_expr: refactor and improve simplification of comparisons
 2019-01-02 17:34:04 +01:00
whitequark
bf8db55ef3 opt_expr: improve simplification of comparisons with large constants. 
The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
 2019-01-02 15:45:28 +00:00
Clifford Wolf
56ca1e6afc
Merge pull request #755 from Icenowy/anlogic-dram-init 
anlogic: implement DRAM initialization
 2019-01-02 16:28:18 +01:00
Clifford Wolf
b236faffa1 Merge branch 'master' of github.com:YosysHQ/yosys 2019-01-02 15:53:50 +01:00
Clifford Wolf
979de95cf6
Merge pull request #750 from Icenowy/anlogic-ff-init 
Initialization of Anlogic DFFs
 2019-01-02 15:52:22 +01:00
Clifford Wolf
2e606b1802
Merge pull request #773 from whitequark/opt_lut_elim_fixes 
opt_lut: elimination fixes
 2019-01-02 15:45:29 +01:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut 
synth: add k-LUT mode
 2019-01-02 15:44:57 +01:00
Clifford Wolf
00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut 
cmp2lut: new techmap pass
 2019-01-02 15:43:10 +01:00
Clifford Wolf
1eb101a38a Improve VerificImporter support for writes to asymmetric memories 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:33:43 +01:00
Clifford Wolf
50b09de033 Fix VerificImporter asymmetric memories error message 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-01-02 15:05:23 +01:00
Clifford Wolf
16bb823db8
Merge pull request #769 from whitequark/typos 
Fix typographical and grammatical errors and inconsistencies
 2019-01-02 14:47:18 +01:00
whitequark
efa278e232 Fix typographical and grammatical errors and inconsistencies. 
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
 2019-01-02 13:12:17 +00:00
whitequark
c55dfb8369 opt_lut: reflect changes in sigmap. 
Otherwise, some LUTs will be missed during elimination.
 2019-01-02 10:21:58 +00:00
whitequark
06143ab33f opt_lut: use a worklist, and revisit cells affected by elimination. 2019-01-02 09:36:32 +00:00
whitequark
f7363ac508 opt_lut: count eliminated cells, and set opt.did_something for them. 2019-01-02 09:14:43 +00:00
whitequark
17b2831356 synth_ice40: use 4-LUT coarse synthesis mode. 2019-01-02 08:25:55 +00:00
whitequark
18174202a9 synth: add k-LUT mode. 2019-01-02 08:25:03 +00:00
whitequark
fdff32dd73 synth: improve script documentation. NFC. 2019-01-02 08:05:44 +00:00
whitequark
a91892bba4 cmp2lut: new techmap pass. 2019-01-02 07:53:31 +00:00
whitequark
4fd458290c opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. 2019-01-02 05:11:29 +00:00
whitequark
9e9846a6ea opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. 2019-01-02 03:01:25 +00:00
whitequark
8e53d2e0bf opt_expr: simplify any unsigned comparisons with all-0 and all-1. 
Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
 2019-01-02 02:45:49 +00:00
Clifford Wolf
4b9f619349
Merge pull request #768 from whitequark/opt_lut_elim 
opt_lut: eliminate LUTs evaluating to constants or inputs
 2019-01-01 11:13:48 +01:00
whitequark
42c356c49c opt_lut: eliminate LUTs evaluating to constants or inputs. 2018-12-31 23:55:40 +00:00
Clifford Wolf
0a840dd883 Fix handling of (* keep *) wires in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-31 16:37:40 +01:00
Clifford Wolf
e09e49ca54
Merge pull request #766 from Icenowy/anlogic-latches 
anlogic: add latch cells
 2018-12-31 15:52:01 +01:00
Larry Doolittle
ebe9351f82 Fix 7 instances of add_share_file to add_gen_share_file 
in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
 2018-12-29 12:53:12 +01:00
Larry Doolittle
99706b3bf4 Squelch a little more trailing whitespace 2018-12-29 12:46:54 +01:00
Icenowy Zheng
1b36944299 anlogic: add latch cells 
Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
 2018-12-25 22:47:46 +08:00
Clifford Wolf
245724a504
Merge pull request #761 from whitequark/proc_clean_partial 
proc_clean: remove any empty cases, if possible to do safely
 2018-12-23 16:16:06 +01:00
Clifford Wolf
6dad191377 Add "read_ilang -[no]overwrite" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-23 15:45:09 +01:00
Clifford Wolf
d938ce7ab6 Merge branch 'master' of github.com:YosysHQ/yosys 2018-12-23 15:44:19 +01:00
whitequark
18291c20d2 proc_clean: remove any empty cases if all cases use all-def compare. 2018-12-23 09:04:30 +00:00