Roland Coeurjoly 
								
							 
						 
						
							
							
							
							
								
							
							
								91e3773b51 
								
							 
						 
						
							
							
								
								Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting  
							
							
							
						 
						
							2024-08-21 14:28:42 +01:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									Jannis Harder 
								
							 
						 
						
							
							
							
							
								
							
							
								b08a880704 
								
							 
						 
						
							
							
								
								backends/rtlil: Do not shorten a value with z bits to 'x  
							
							
							
						 
						
							2023-01-29 14:02:25 +01:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									Miodrag Milanovic 
								
							 
						 
						
							
							
							
							
								
							
							
								6574553189 
								
							 
						 
						
							
							
								
								Fixes for some of clang scan-build detected issues  
							
							
							
						 
						
							2023-01-17 12:58:08 +01:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									Miodrag Milanovic 
								
							 
						 
						
							
							
							
							
								
							
							
								99f1c71582 
								
							 
						 
						
							
							
								
								properly encode string in rtlil  
							
							
							
						 
						
							2022-08-09 12:45:32 +02:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									Marcelina Kościelnicka 
								
							 
						 
						
							
							
							
							
								
							
							
								d019b4e681 
								
							 
						 
						
							
							
								
								rtlil: Dump empty connections when whole module is selected.  
							
							... 
							
							
							
							Without this, empty connections will be always skipped by `dump`, since
they contain no selected wires.  This makes debugging rather confusing. 
							
						 
						
							2021-12-12 01:22:06 +01:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									Claire Xenia Wolf 
								
							 
						 
						
							
							
							
							
								
							
							
								89df26e4bc 
								
							 
						 
						
							
							
								
								Add optimization to rtlil back-end for all-x parameter values  
							
							... 
							
							
							
							Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> 
							
						 
						
							2021-09-27 16:02:20 +02:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									Claire Xenia Wolf 
								
							 
						 
						
							
							
							
							
								
							
							
								72787f52fc 
								
							 
						 
						
							
							
								
								Fixing old e-mail addresses and deadnames  
							
							... 
							
							
							
							s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g ; 
							
						 
						
							2021-06-08 00:39:36 +02:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									Marcelina Kościelnicka 
								
							 
						 
						
							
							
							
							
								
							
							
								192601385f 
								
							 
						 
						
							
							
								
								rtlil: Fix process memwr roundtrip.  
							
							... 
							
							
							
							Fixes  #2646  fallout. 
						
							2021-03-23 19:49:47 +01:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									Marcelina Kościelnicka 
								
							 
						 
						
							
							
							
							
								
							
							
								4e03865d5b 
								
							 
						 
						
							
							
								
								Add support for memory writes in processes.  
							
							
							
						 
						
							2021-03-08 20:16:29 +01:00 
							
								 
							
							
								 
							
						 
					 
				
					
						
							
								
								
									whitequark 
								
							 
						 
						
							
							
							
							
								
							
							
								00e7dec7f5 
								
							 
						 
						
							
							
								
								Replace "ILANG" with "RTLIL" everywhere.  
							
							... 
							
							
							
							The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility. 
							
						 
						
							2020-08-26 17:29:32 +00:00