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53 commits

Author SHA1 Message Date
whitequark
00e7dec7f5 Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.

Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
whitequark
2ffdb74fb1 Use (and ignore) the expression provided to log_assert in NDEBUG builds.
This avoids warnings in NDEBUG builds emitted when a variable is only
used in log_assert, but is always defined.
2020-06-19 15:48:58 +00:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Vamsi K Vytla
5f9cd2e2f6 Preserve 'signed'-ness of a verilog wire through RTLIL
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:

RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
Marcelina Kościelnicka
06a344efcb ilang, ast: Store parameter order and default value information.
Fixes #1819, #1820.
2020-04-21 19:09:00 +02:00
Alberto Gonzalez
68fef4ca7f
Clean up pseudo-private member usage in backends/ilang/ilang_backend.cc. 2020-04-01 03:08:39 +00:00
Eddie Hung
7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
whitequark
93bc5affd3 Allow attributes on individual switch cases in RTLIL.
The parser changes are slightly awkward. Consider the following IL:

    process $0
      <point 1>
      switch \foo
        <point 2>
        case 1'1
          assign \bar \baz
          <point 3>
          ...
        case
      end
    end

Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.

To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.

Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
Ben Widawsky
4a18e19fb8 Support filename rewrite in backends
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-18 14:39:52 -07:00
Clifford Wolf
1cd1b5fc1a Add "real" keyword to ilang format
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:00:40 +02:00
Clifford Wolf
04e920337b Fix a syntax bug in ilang backend related to process case statements
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 17:50:20 +01:00
Henner Zeller
3aa4484a3c Consistent use of 'override' for virtual methods in derived classes.
o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
e4f0218907 Fixed gcc 7.2 "statement will never be executed" warning 2018-02-03 14:31:47 +01:00
Clifford Wolf
aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf
53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf
0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
fb8c755726 Shorter "dump" options 2015-01-31 23:52:36 +01:00
Clifford Wolf
2a9ad48eb6 Added ENABLE_NDEBUG makefile options 2015-01-24 12:16:46 +01:00
Clifford Wolf
43951099cf Added dict/pool.sort() 2015-01-24 00:13:27 +01:00
Clifford Wolf
eefe78be09 Fixed memory->start_offset handling 2015-01-01 12:56:01 +01:00
Clifford Wolf
9e6fb0b02c Replaced std::unordered_map as implementation for Yosys::dict 2014-12-26 21:35:22 +01:00
Clifford Wolf
f9a307a50b namespace Yosys 2014-09-27 16:17:53 +02:00
Clifford Wolf
309623ff17 Sorting of object names in ilang backend 2014-09-19 15:50:34 +02:00
Clifford Wolf
5dce303a2a Changed backend-api from FILE to std::ostream 2014-08-23 13:54:21 +02:00
Clifford Wolf
1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf
3c45277ee0 Added wire->upto flag for signals such as "wire [0:7] x;" 2014-07-28 12:12:13 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
10e5791c5e Refactoring: Renamed RTLIL::Design::modules to modules_ 2014-07-27 11:18:30 +02:00
Clifford Wolf
4c4b602156 Refactoring: Renamed RTLIL::Module::cells to cells_ 2014-07-27 01:51:45 +02:00
Clifford Wolf
f9946232ad Refactoring: Renamed RTLIL::Module::wires to wires_ 2014-07-27 01:49:51 +02:00
Clifford Wolf
b7dda72302 Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf
5826670009 Various RTLIL::SigSpec related code cleanups 2014-07-25 14:25:42 +02:00
Clifford Wolf
6aa792c864 Replaced more old SigChunk programming patterns 2014-07-24 23:10:58 +02:00
Clifford Wolf
4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf
4147b55c23 Added "autoidx" statement to ilang file format 2014-07-21 15:15:18 +02:00
Clifford Wolf
fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
Clifford Wolf
968ae31cac Added support for dump -append 2014-02-04 23:45:30 +01:00
Clifford Wolf
74d0de3b74 Updated manual/command-reference-manual.tex 2013-12-28 12:14:47 +01:00
Clifford Wolf
f4b46ed31e Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
Clifford Wolf
93a70959f3 Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
Clifford Wolf
ed441346ca Added dump -m and -n options 2013-11-29 10:33:36 +01:00
Clifford Wolf
0ef22c7609 Added support for signed parameters in ilang 2013-11-24 17:37:27 +01:00
Clifford Wolf
f71e27dbf1 Remove auto_wire framework (smarter than the verilog standard) 2013-11-24 17:29:11 +01:00
Clifford Wolf
09471846c5 Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
Clifford Wolf
1dcb683fcb Write yosys version to output files 2013-11-03 21:41:39 +01:00
Clifford Wolf
73914d1a41 Added -selected option to various backends 2013-09-03 19:10:11 +02:00
Clifford Wolf
af79b4bd98 Fixed generation of newlines in "dump" output 2013-06-10 12:38:02 +02:00