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11374 commits 122 branches 59 tags 72 MiB
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Author SHA1 Message Date
Claire Wolf
7112f187cd Add missing .gitignore file 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 22:25:47 +02:00
Yehowshua Immanuel
5d29a9f633
MacOS has even stricter stack limits in catalina. 
Invoking sby in macOS Catalina fails because of bizarre stack limits in Catalina.
 2020-06-04 14:01:56 -04:00
clairexen
352731df4e
Merge pull request #2041 from PeterCrozier/struct 
Implementation of  SV structs.
 2020-06-04 18:26:07 +02:00
clairexen
ba99c0ea81
Merge pull request #2099 from Xiretza/manual-include-path 
Use in-tree include directory in manual build
 2020-06-04 18:23:33 +02:00
N. Engelhardt
d8d8deeaf4
Add codeowners file (#2098) 2020-06-04 18:20:08 +02:00
Eddie Hung
69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
 2020-06-04 08:15:25 -07:00
N. Engelhardt
82798ae575 btor backend: make not printing internal names default 2020-06-04 16:24:16 +02:00
Claire Wolf
5e8a9c61cd Add printf format attributes to btorf/infof helper functions 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-06-04 15:53:28 +02:00
clairexen
8efe6ee7f5
Merge pull request #2108 from nakengelhardt/btor_internal_names 
btor backend: add option to not include internal names
 2020-06-04 15:48:40 +02:00
whitequark
5a5a9b4ffe flatten: clean up log messages. 2020-06-04 12:22:59 +00:00
whitequark
d731fe054b flatten: topologically sort modules. 2020-06-04 12:22:59 +00:00
N. Engelhardt
8ceb6686e0 btor backend: add option to not include internal names 2020-06-04 14:00:52 +02:00
whitequark
3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire 
Preserve 'signed'-ness of a verilog wire through RTLIL
 2020-06-04 11:23:06 +00:00
N. Engelhardt
44f1e65155
Merge pull request #2070 from hackfin/master 
Pyosys API: idict type handling
 2020-06-04 11:17:08 +02:00
Eddie Hung
45cd323055
Merge pull request #2082 from YosysHQ/eddie/abc9_scc_fixes 
abc9: fixes around handling combinatorial loops
 2020-06-03 17:35:46 -07:00
whitequark
6268bdfe6f flatten: simplify. 
`flatten` cannot derive modules in most cases because that would just
yield processes, and it does not support `-autoproc`; in practice
`flatten` has to be preceded by a call to `hierarchy`, which makes
deriving unnecessary.
 2020-06-04 00:02:12 +00:00
whitequark
d3e2100306 flatten: simplify. NFC. 
Remove redundant sigmaps.
 2020-06-04 00:02:12 +00:00
whitequark
66255dab4e flatten: simplify. 
Flattening does not benefit from topologically sorting cells within
a module when processing them.
 2020-06-04 00:02:12 +00:00
whitequark
5d2b6d1394 flatten: simplify. NFC. 
Flatten is non-recursive and doesn't need to keep track of handled
cells.
 2020-06-04 00:02:12 +00:00
whitequark
3c3fa774e5 flatten: simplify. NFC. 
Flattening always does "non-recursive" mapping.
 2020-06-04 00:02:12 +00:00
whitequark
e561a3a76f flatten: simplify. NFC. 
The `celltypeMap` always maps `x` to `{x}`.
 2020-06-04 00:02:12 +00:00
whitequark
6783876807 flatten: simplify. NFC. 
The `design` and `map` designs are always the same when flattening.
 2020-06-04 00:02:12 +00:00
whitequark
9338ff66b9 RTLIL: factor out RTLIL::Module::addMemory. NFC. 2020-06-04 00:02:12 +00:00
whitequark
ebbbe2156e flatten: rename techmap-related stuff. NFC. 2020-06-04 00:02:12 +00:00
whitequark
76c4ee4ea5 techmap, flatten: remove dead options. 
After splitting the passes, some options can never be activated,
and most conditions involving them become dead. Remove them, and also
all of the newly dead code.
 2020-06-04 00:02:12 +00:00
Peter Crozier
0d3f7ea011
Merge branch 'master' into struct 2020-06-03 17:19:28 +01:00
Eddie Hung
8a11019d38 tests: tidy up testcase 2020-06-03 08:41:55 -07:00
Eddie Hung
46ed0db2ec
Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings 
tests: reduce test warnings
 2020-06-03 08:37:07 -07:00
whitequark
6ac54a74fe flatten: split from techmap. 
Although the two passes started out very similar, they diverged over
time and now have little in common. Moreover, `techmap` is extremely
complex while `flatten` does not have to be, and this complexity
interferes with improving `flatten`.
 2020-06-03 15:34:03 +00:00
whitequark
577859fbdb
Merge pull request #2104 from whitequark/simplify-techmap 
techmap: simplify
 2020-06-03 12:45:02 +00:00
whitequark
fb5b070e7e techmap: remove dead variable. NFC. 2020-06-03 01:44:06 +00:00
whitequark
0a74368bfc techmap: use C++11 default member initializers. NFC. 2020-06-02 23:43:20 +00:00
whitequark
f3e86bb32a techmap: simplify. 
`rewrite_filename` is already called in `Frontend::extra_args`.
 2020-06-02 23:43:20 +00:00
whitequark
68d747f767 techmap: use +/techmap.v instead of an ad-hoc code generator. 2020-06-02 23:43:20 +00:00
clairexen
4b3f48a7ec
Merge pull request #2102 from YosysHQ/tests_fix 
allow range for mux test
 2020-06-02 17:13:08 +02:00
clairexen
2ed045738b
Merge pull request #2101 from YosysHQ/mmicko/verific_asymmetric 
Support asymmetric memories for verific frontend
 2020-06-02 17:12:02 +02:00
Miodrag Milanovic
0a88f002e5 allow range for mux test 2020-06-01 13:48:19 +02:00
Miodrag Milanovic
71072d1945 Support asymmetric memories for verific frontend 2020-06-01 10:30:03 +02:00
clairexen
ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap 
Clean up `passes/techmap/techmap.cc`
 2020-05-31 20:40:48 +02:00
Eddie Hung
08d9703ecb abc9_ops: fix comment 2020-05-30 09:01:03 -07:00
Eddie Hung
fe273faad1
Merge pull request #2081 from YosysHQ/eddie/blackbox_ast 
blackbox: use Module::makeblackbox() method
 2020-05-30 08:59:20 -07:00
Eddie Hung
ea4374a223 abc9_ops: update messaging (credit to @Xiretza for spotting) 2020-05-30 08:57:48 -07:00
clairexen
ea46ed81f9
Merge pull request #2018 from boqwxp/qbfsat-timeout 
smtbmc and qbfsat: Add timeout option to set solver timeouts for Z3, Yices, and CVC4.
 2020-05-30 15:04:51 +02:00
Xiretza
8b0ec3c3a2
Use in-tree include directory in manual build 
This is basically the same issue as in tests/various/plugin.sh,
which uses yosys-config to compile a plugin. `yosys-config --cxxflags`
points to `$PREFIX/share/` (/usr/local/share by default), which might
not exist yet or might be out of date. Building directly from the
headers in ./share/ avoids this.
 2020-05-30 11:21:40 +02:00
Eddie Hung
b17e8495b8 abc9_ops: optimise to not derive unless attribute exists 2020-05-29 17:33:10 -07:00
Eddie Hung
d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
Alberto Gonzalez
ea30465107
smtbmc: Remove superfluous yosys-smt2-timeout file macro. 
Co-Authored-By: clairexen <claire@symbioticeda.com>
 2020-05-29 21:33:00 +00:00
clairexen
0a14e1e837
Merge pull request #2029 from whitequark/fix-simplify-memory-sv_logic 
ast/simplify: don't bitblast async ROMs declared as `logic`
 2020-05-29 16:52:11 +02:00
clairexen
94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells 
Fix modulo/remainder semantics
 2020-05-29 16:37:23 +02:00
clairexen
af36afe722
Merge pull request #2092 from whitequark/rtlil-no-space-control 
Restrict RTLIL::IdString to not contain whitespace or control chars
 2020-05-29 16:31:44 +02:00