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8 commits

Author SHA1 Message Date
Eddie Hung
cd7b2de27f WIP for cells_map.v -- maybe working? 2019-04-10 18:05:09 -07:00
Eddie Hung
3d577586fd Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 2019-04-10 16:15:23 -07:00
Eddie Hung
3f5dab0d09 Fix for when B_SIGNED = 1 2019-04-10 14:51:10 -07:00
Eddie Hung
1ec949d5ed Tidy up 2019-04-10 09:02:42 -07:00
Eddie Hung
e0b46eb4cb WIP for $shiftx to wide mux 2019-04-10 08:49:55 -07:00
Keith Rothman
3090951d54 Changes required for VPR place and route synth_xilinx. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-03-01 12:02:27 -08:00
Tim 'mithro' Ansell
d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Clifford Wolf
d29d26f882 Various cleanups in xilinx techlib 2015-01-18 19:43:54 +01:00
Renamed from techlibs/xilinx/cells.v (Browse further)