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Code Activity
14281 commits 122 branches 59 tags 72 MiB
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1376 commits

Author SHA1 Message Date
Akash Levy
285c8a3f66
Merge branch 'YosysHQ:main' into main 2024-09-12 11:14:15 -07:00
github-actions[bot]
229d1ea937 Bump version 2024-09-12 00:19:38 +00:00
Akash Levy
02931ebfd2
Merge branch 'YosysHQ:main' into main 2024-09-10 11:23:27 -07:00
github-actions[bot]
6937241012 Bump version 2024-09-10 00:19:34 +00:00
Akash Levy
7ff3bff014 Add tee 2024-09-09 12:34:43 -07:00
Akash Levy
d427b78afd
Merge branch 'YosysHQ:main' into main 2024-09-09 10:16:51 -07:00
github-actions[bot]
dcf9f58315 Bump version 2024-09-07 00:18:42 +00:00
Akash Levy
74c26a8418 Try to disable func 2024-09-06 08:08:38 -07:00
Akash Levy
20c5ed2ebb Merge latest 2024-09-06 07:43:14 -07:00
Miodrag Milanović
b20df72e1e
Merge pull request #4536 from YosysHQ/functional 
Functional Backend
 2024-09-06 10:05:04 +02:00
Miodrag Milanovic
fc10a6eee2 Run functional tests on private runner only 2024-09-06 08:47:43 +02:00
Akash Levy
b443ff5f05 Fix 2024-09-05 22:32:12 -07:00
Akash Levy
1d2a4116c2 Try again 2024-09-05 22:28:43 -07:00
Akash Levy
c4c4fe603f Smallfix 2024-09-05 22:21:20 -07:00
Akash Levy
cc3acb9894 Fix whereami extension 2024-09-05 22:13:28 -07:00
Akash Levy
18f05ba615 Add those CXXFLAGS 2024-09-05 22:10:04 -07:00
github-actions[bot]
e8951aba29 Bump version 2024-09-06 00:19:21 +00:00
Akash Levy
cd56f7f7b4 Add setattr to Makefile SMALL 2024-09-05 17:05:54 -07:00
Akash Levy
10c9e27433 Add yosys-slang 2024-09-05 15:22:31 -07:00
Akash Levy
ce95ec1f9e Add VHDL support via GHDL call 2024-09-05 13:24:38 -07:00
Akash Levy
42dc3f6da6 Add splitcells and splitnets 2024-09-04 21:54:39 -07:00
Krystine Sherwin
21494d1f06
Makefile: Update coverage_functional 
Note sure if this is the best way to do it, but it works?
 2024-09-05 11:43:42 +12:00
Emily Schmidt
5a476a8d29 functional tests: run from make tests but not smtlib/rkt tests 2024-09-04 10:30:08 +01:00
Akash Levy
120f69eda7
Merge branch 'YosysHQ:main' into main 2024-09-04 00:02:25 -07:00
github-actions[bot]
d567164173 Bump version 2024-09-04 00:19:13 +00:00
Miodrag Milanovic
0744fac883 Next dev cycle 2024-09-03 12:39:38 +02:00
Miodrag Milanovic
3e0dc2ff1e Release version 0.45 2024-09-03 10:28:56 +02:00
Miodrag Milanović
598d010349
Merge pull request #4504 from YosysHQ/nanoxplore 
NanoXplore synthesis
 2024-09-03 10:19:44 +02:00
Miodrag Milanović
9fca352882
Merge pull request #4563 from YosysHQ/krys/better_rtds_action 
Better docs builds
 2024-09-03 09:32:24 +02:00
github-actions[bot]
6b9321250b Bump version 2024-09-03 00:20:12 +00:00
Krystine Sherwin
cab781d958
Makefile: Move docs prereqs to separate target 2024-09-03 11:30:59 +12:00
Akash Levy
81e4f0aaed Add check 2024-09-01 21:58:13 -07:00
Akash Levy
2c9c6e693f Add muxadd peepopt 2024-08-30 04:45:01 -07:00
Emily Schmidt
2b8db94aa0 functional backend: add test to verify test_generic 2024-08-29 13:14:18 +01:00
Akash Levy
4f6a153961 Working tree balance pass 2024-08-27 08:19:17 -07:00
Akash Levy
f707a3b6cd
Merge branch 'YosysHQ:main' into main 2024-08-26 22:37:42 -07:00
Akash Levy
243d8317a5 SMALL mode with first pass of opt_balance_tree 2024-08-26 22:36:47 -07:00
Krystine Sherwin
0b53b10770
Makefile: Stop unconditionally install docs prereqs 2024-08-27 10:06:25 +12:00
github-actions[bot]
72f77dd97b Bump version 2024-08-23 00:18:22 +00:00
Akash Levy
57446f3f93
Merge branch 'YosysHQ:main' into master 2024-08-21 18:52:38 -07:00
github-actions[bot]
27b51cb351 Bump version 2024-08-22 00:18:24 +00:00
Emily Schmidt
850b3a6c29 convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h 2024-08-21 11:04:08 +01:00
Emily Schmidt
00a65754bb factor out SExpr/SExprWriter classes out of smtlib backend, and also tidy them up/document them 2024-08-21 11:03:27 +01:00
Miodrag Milanovic
e296b884d5 Add Makefile helpers for coverage 2024-08-21 11:02:31 +01:00
Emily Schmidt
6f9e21219b add new generic compute graph and rewrite c++ functional backend to use it 2024-08-21 11:02:29 +01:00
Jannis Harder
56572978f5 drivertools: Utility code for indexing and traversing signal drivers 
It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar
to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent
cell ports, undriven bits and multiple drivers. For indexing an RTLIL
module and for querying signal drivers it comes with a `DriverMap` type
which is somewhat similar to a `SigMap` but is guaranteed to produce
signal drivers as returned representatives.

A `DriverMap` can also optionally preserve connections via intermediate
wires (e.g. querying the driver of a cell input port will return a
connected intermediate wire, querying the driver of that wire will
return the cell output port that's driving the wire).
 2024-08-21 11:00:21 +01:00
Akash Levy
e2957936e4
Merge branch 'YosysHQ:main' into master 2024-08-20 01:38:01 -07:00
github-actions[bot]
4cddc19994 Bump version 2024-08-20 00:18:24 +00:00
Akash Levy
56cfcdb9f6
Merge branch 'YosysHQ:main' into master 2024-08-19 17:12:02 -07:00
N. Engelhardt
7f08a298a4
Merge pull request #4542 from YosysHQ/krys/rtd 
Local readthedocs
 2024-08-19 10:04:38 +02:00