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Author	SHA1	Message	Date
Clifford Wolf	8836943693	Added yet another resource sharing test case	2014-07-20 21:15:01 +02:00
Clifford Wolf	04fcb07213	Added support for resource sharing in mux control logic	2014-07-20 20:44:14 +02:00
Clifford Wolf	1ce5e83555	Added "select -assert-count"	2014-07-20 20:15:49 +02:00
Clifford Wolf	e9506bb2da	Supercell creation for $div/$mod worked all along, fixed test benches	2014-07-20 18:54:06 +02:00
Clifford Wolf	7a6d578b81	Improved tests/share/generate.py	2014-07-20 17:06:57 +02:00
Clifford Wolf	ff28029fdb	Fixed creation of shift supercells in "share" pass	2014-07-20 17:06:36 +02:00
Clifford Wolf	4af8d84f01	Small fix in tests/vloghtb/run-test.sh	2014-07-20 17:05:20 +02:00
Clifford Wolf	dd23e9a9db	Activated tests/share in "make test"	2014-07-20 15:33:07 +02:00
Clifford Wolf	4c38ec1cc8	Added "miter -equiv -flatten"	2014-07-20 15:33:07 +02:00
Clifford Wolf	8d04ca7d22	Added call_on_selection() and call_on_module() API	2014-07-20 15:33:06 +02:00
Clifford Wolf	2e358bd667	Added tests/vloghtb/test_share.sh	2014-07-20 15:33:05 +02:00
Clifford Wolf	6f450d0224	Added tests/share for testing "share" supercell creation	2014-07-20 15:32:59 +02:00
Clifford Wolf	5b3ee7a072	Added "share" supercell creation	2014-07-20 15:01:17 +02:00
Clifford Wolf	7b98e46ac3	Added removing of always inactive cells to "share" pass	2014-07-20 13:24:36 +02:00
Clifford Wolf	8819493db4	Progress in "share" pass	2014-07-20 11:04:52 +02:00
Clifford Wolf	e57db5e9b2	Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion	2014-07-20 11:01:04 +02:00
Clifford Wolf	efa7884026	Added SIZE() macro	2014-07-20 10:36:14 +02:00
Clifford Wolf	a6174aaf5e	Added log_cell()	2014-07-20 10:35:47 +02:00
Clifford Wolf	15fd615da5	Progress in "share" pass	2014-07-20 03:03:04 +02:00
Clifford Wolf	3f9f0c047d	Added tests/vloghtb	2014-07-20 02:19:44 +02:00
Clifford Wolf	a30e2857c7	Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog backend	2014-07-20 02:16:30 +02:00
Clifford Wolf	0c67393313	Added support for $bu0 to verilog backend	2014-07-20 01:56:16 +02:00
Clifford Wolf	2278995bd8	Started to implement real resource sharing	2014-07-19 20:54:32 +02:00
Clifford Wolf	02f0acb3bc	Fixed log_id() memory corruption	2014-07-19 20:53:29 +02:00
Clifford Wolf	efd9604dfb	Improved memory_share log messages	2014-07-19 15:46:11 +02:00
Clifford Wolf	e0a819dbe5	More verbose memory_share help message	2014-07-19 15:34:14 +02:00
Clifford Wolf	297a0962ea	Added SAT-based write-port sharing to memory_share	2014-07-19 15:33:55 +02:00
Clifford Wolf	35edac0b31	Added ModWalker helper class	2014-07-19 15:33:00 +02:00
Clifford Wolf	1c288adcc0	Some "const" cleanups in SigMap	2014-07-19 15:32:39 +02:00
Clifford Wolf	26f982ac0b	Fixed bug in memory_share feedback-to-en code	2014-07-19 15:32:14 +02:00
Clifford Wolf	e441f07d89	Added translation from read-feedback to en-signals in memory_share	2014-07-18 16:46:40 +02:00
Clifford Wolf	44f13aff92	Improved seeding of color rng in show command	2014-07-18 16:44:45 +02:00
Clifford Wolf	a341931972	Only create collision detect logic in memory_share if necessary	2014-07-18 14:32:40 +02:00
Clifford Wolf	ddb01df42e	Bugfix in tests/memories/run-test.sh	2014-07-18 13:45:25 +02:00
Clifford Wolf	5d9127418b	added tests/memories	2014-07-18 13:25:19 +02:00
Clifford Wolf	ab4b26679f	Added memory_share	2014-07-18 13:16:56 +02:00
Clifford Wolf	a721f7d768	Added automatic conversion from RTLIL::SigSpec to std::vector<RTLIL::SigBit>	2014-07-18 11:36:34 +02:00
Clifford Wolf	309ae98246	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	2014-07-18 10:28:45 +02:00
Clifford Wolf	2d69c309f9	Added function-like cell creation helpers	2014-07-18 10:27:06 +02:00
Clifford Wolf	a8cedb2257	Added log_id() helper function	2014-07-18 10:26:01 +02:00
Clifford Wolf	ec3a798194	Also simulate unmapped memories in "make test"	2014-07-17 16:53:52 +02:00
Clifford Wolf	9b183539af	Implemented dynamic bit-/part-select for memory writes	2014-07-17 16:49:23 +02:00
Clifford Wolf	f1ca93a0a3	Fixed simlib.v model for $mem	2014-07-17 16:48:36 +02:00
Clifford Wolf	5867f6bcdc	Added support for bit/part select to mem2reg rewriter	2014-07-17 13:49:32 +02:00
Clifford Wolf	6d69d4aaa8	Added support for constant bit- or part-select for memory writes	2014-07-17 13:13:21 +02:00
Clifford Wolf	1b00861d0a	Improved opt_reduce handling of mem wr_en mux bits	2014-07-17 12:12:04 +02:00
Clifford Wolf	274c514879	Fixed RTLIL::SigSpec::append_bit() for appending constants	2014-07-17 12:10:57 +02:00
Clifford Wolf	b76bf05cda	Added support for "blackbox" attribute to iopadmap	2014-07-17 08:59:07 +02:00
Clifford Wolf	64a6906cc4	Added support for "blackbox" attribute to flatten/techmap	2014-07-17 08:58:51 +02:00
Clifford Wolf	b171a4c1bc	Added "inout" ports support to read_liberty	2014-07-16 18:12:46 +02:00