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https://github.com/YosysHQ/yosys
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Progress in "share" pass
This commit is contained in:
Clifford Wolf
parent
e57db5e9b2
commit
8819493db4
1 changed files with 185 additions and 112 deletions
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@ -38,9 +38,77 @@ struct ShareWorker
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RTLIL::Design *design;
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RTLIL::Module *module;
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CellTypes cone_ct;
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CellTypes fwd_ct, cone_ct;
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ModWalker modwalker;
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// ------------------------------------------------------------------------------
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// Find terminal bits -- i.e. bits that do not (exclusively) feed into a mux tree
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// ------------------------------------------------------------------------------
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std::set<RTLIL::SigBit> terminal_bits;
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void find_terminal_bits()
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{
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std::set<RTLIL::SigBit> queue_strong_bits, queue_weak_bits;
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std::set<RTLIL::Cell*> visited_cells;
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queue_weak_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end());
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for (auto &it : module->cells)
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{
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RTLIL::Cell *cell = it.second;
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if (cell->type == "$mux" || cell->type == "$pmux")
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{
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std::vector<RTLIL::SigBit> bits = modwalker.sigmap(cell->connections.at("\\S"));
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queue_strong_bits.insert(bits.begin(), bits.end());
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}
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else if (!fwd_ct.cell_known(cell->type))
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{
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std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[cell];
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queue_weak_bits.insert(bits.begin(), bits.end());
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}
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}
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terminal_bits.insert(queue_strong_bits.begin(), queue_strong_bits.end());
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terminal_bits.insert(queue_weak_bits.begin(), queue_weak_bits.end());
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while (!queue_strong_bits.empty())
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{
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std::set<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, queue_strong_bits);
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queue_strong_bits.clear();
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for (auto &pbit : portbits)
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if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
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std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
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terminal_bits.insert(bits.begin(), bits.end());
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queue_strong_bits.insert(bits.begin(), bits.end());
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visited_cells.insert(pbit.cell);
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}
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}
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while (!queue_weak_bits.empty())
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{
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std::set<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, queue_weak_bits);
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queue_weak_bits.clear();
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for (auto &pbit : portbits) {
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if (pbit.cell->type == "$mux" || pbit.cell->type == "$pmux")
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continue;
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if (fwd_ct.cell_known(pbit.cell->type) && visited_cells.count(pbit.cell) == 0) {
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std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[pbit.cell];
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terminal_bits.insert(bits.begin(), bits.end());
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queue_weak_bits.insert(bits.begin(), bits.end());
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visited_cells.insert(pbit.cell);
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}
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}
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}
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}
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// ---------------------------------------------------
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// Find shareable cells and compatible groups of cells
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// ---------------------------------------------------
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@ -49,8 +117,6 @@ struct ShareWorker
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void find_shareable_cells()
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{
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std::vector<RTLIL::Cell*> candidates;
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for (auto &it : module->cells)
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{
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RTLIL::Cell *cell = it.second;
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@ -58,50 +124,43 @@ struct ShareWorker
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if (!design->selected(module, cell) || !modwalker.ct.cell_known(cell->type))
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continue;
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for (auto &bit : modwalker.cell_outputs[cell])
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if (terminal_bits.count(bit))
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goto not_a_muxed_cell;
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if (0)
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not_a_muxed_cell:
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continue;
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if (config.opt_force) {
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candidates.push_back(cell);
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type == "$memrd") {
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if (!cell->parameters.at("\\CLK_ENABLE").as_bool())
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candidates.push_back(cell);
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 4)
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candidates.push_back(cell);
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 8)
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candidates.push_back(cell);
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type == "$add" || cell->type == "$sub") {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 10)
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candidates.push_back(cell);
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shareable_cells.insert(cell);
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continue;
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}
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}
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for (auto cell : candidates)
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{
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std::set<ModWalker::PortBit> driven_bits;
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modwalker.get_consumers(driven_bits, modwalker.cell_outputs[cell]);
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for (auto bit : driven_bits) {
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if (bit.cell->type != "$mux" && bit.cell->type != "$pmux")
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goto skip_candidate;
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if (bit.port != "\\A" && bit.port != "\\B")
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goto skip_candidate;
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}
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if (!modwalker.has_outputs(modwalker.cell_outputs[cell]))
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shareable_cells.insert(cell);
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skip_candidate:;
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}
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}
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bool is_shareable_pair(RTLIL::Cell *c1, RTLIL::Cell *c2)
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@ -170,77 +229,28 @@ struct ShareWorker
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std::map<RTLIL::Cell*, std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>>> activation_patterns_cache;
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void follow_mux_data_cone(std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &patterns,
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std::set<std::pair<RTLIL::SigBit, RTLIL::State>> &state, RTLIL::SigSpec signal)
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bool sort_check_pattern(std::pair<RTLIL::SigSpec, RTLIL::Const> &p)
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{
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std::set<ModWalker::PortBit> consumers;
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std::map<RTLIL::Cell*, std::set<ModWalker::PortBit>> consumers_by_cell;
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std::map<RTLIL::SigBit, RTLIL::State> p_bits;
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if (modwalker.has_outputs(signal))
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goto signal_outside_mux_tree;
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modwalker.get_consumers(consumers, signal);
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for (auto &bit : consumers) {
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if ((bit.cell->type != "$mux" && bit.cell->type != "$pmux") || bit.port == "\\S")
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goto signal_outside_mux_tree;
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consumers_by_cell[bit.cell].insert(bit);
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std::vector<RTLIL::SigBit> p_first_bits = p.first;
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for (int i = 0; i < SIZE(p_first_bits); i++) {
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RTLIL::SigBit b = p_first_bits[i];
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RTLIL::State v = p.second.bits[i];
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if (p_bits.count(b) && p_bits.at(b) != v)
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return false;
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p_bits[b] = v;
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}
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if (0) {
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signal_outside_mux_tree:;
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RTLIL::SigSpec pattern_first, pattern_second;
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for (auto &bit : state) {
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pattern_first.append_bit(bit.first);
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pattern_second.append_bit(bit.second);
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}
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patterns.insert(std::pair<RTLIL::SigSpec, RTLIL::Const>(pattern_first, pattern_second.as_const()));
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return;
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p.first = RTLIL::SigSpec();
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p.second.bits.clear();
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for (auto &it : p_bits) {
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p.first.append_bit(it.first);
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p.second.bits.push_back(it.second);
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}
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for (auto &it : consumers_by_cell)
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{
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RTLIL::Cell *cell = it.first;
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log_assert(cell->type == "$mux" || cell->type == "$pmux");
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int width = cell->parameters.at("\\WIDTH").as_int();
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std::set<int> used_in_b_parts;
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bool used_in_a = false;
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for (auto &bit : it.second) {
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if (bit.port == "\\A")
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used_in_a = true;
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else if (bit.port == "\\B")
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used_in_b_parts.insert(bit.offset / width);
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else
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log_abort();
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}
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std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(cell->connections.at("\\S")).to_sigbit_vector();
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if (used_in_a) {
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std::set<std::pair<RTLIL::SigBit, RTLIL::State>> new_state = state;
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for (auto &bit : sig_s) {
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std::pair<RTLIL::SigBit, RTLIL::State> this_state(bit, RTLIL::State::S0);
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std::pair<RTLIL::SigBit, RTLIL::State> this_inv_state(bit, RTLIL::State::S1);
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if (new_state.count(this_inv_state))
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goto conflict_in_a_port;
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new_state.insert(this_state);
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}
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follow_mux_data_cone(patterns, new_state, modwalker.sigmap(cell->connections.at("\\Y")));
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conflict_in_a_port:;
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}
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for (int part_idx : used_in_b_parts) {
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std::set<std::pair<RTLIL::SigBit, RTLIL::State>> new_state = state;
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std::pair<RTLIL::SigBit, RTLIL::State> this_state(sig_s.at(part_idx), RTLIL::State::S1);
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std::pair<RTLIL::SigBit, RTLIL::State> this_inv_state(sig_s.at(part_idx), RTLIL::State::S0);
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if (new_state.count(this_inv_state))
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goto conflict_in_b_port;
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new_state.insert(this_state);
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follow_mux_data_cone(patterns, new_state, modwalker.sigmap(cell->connections.at("\\Y")));
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conflict_in_b_port:;
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}
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}
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return true;
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}
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const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &find_cell_activation_patterns(RTLIL::Cell *cell)
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@ -248,14 +258,68 @@ struct ShareWorker
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if (activation_patterns_cache.count(cell))
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return activation_patterns_cache.at(cell);
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std::set<std::pair<RTLIL::SigBit, RTLIL::State>> state;
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RTLIL::SigSpec cell_output_signal;
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const std::set<RTLIL::SigBit> &cell_out_bits = modwalker.cell_outputs[cell];
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std::set<RTLIL::Cell*> driven_cells;
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for (auto &bit : modwalker.cell_outputs[cell])
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cell_output_signal.append_bit(bit);
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for (auto &bit : cell_out_bits)
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{
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if (terminal_bits.count(bit)) {
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// Terminal cells are always active: unconditional activation pattern
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activation_patterns_cache[cell].insert(std::pair<RTLIL::SigSpec, RTLIL::Const>());
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return activation_patterns_cache.at(cell);
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}
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for (auto &pbit : modwalker.signal_consumers[bit]) {
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log_assert(fwd_ct.cell_known(pbit.cell->type));
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driven_cells.insert(pbit.cell);
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}
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}
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follow_mux_data_cone(activation_patterns_cache[cell], state, cell_output_signal);
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return activation_patterns_cache.at(cell);
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for (auto c : driven_cells)
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{
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const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &c_patterns = find_cell_activation_patterns(c);
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if (c->type == "$mux" || c->type == "$pmux")
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{
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bool used_in_a = false;
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std::set<int> used_in_b_parts;
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int width = c->parameters.at("\\WIDTH").as_int();
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std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->connections.at("\\A"));
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std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->connections.at("\\B"));
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std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->connections.at("\\S"));
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for (auto &bit : sig_a)
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if (cell_out_bits.count(bit))
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used_in_a = true;
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for (int i = 0; i < SIZE(sig_b); i++)
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if (cell_out_bits.count(sig_b[i]))
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used_in_b_parts.insert(i / width);
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if (used_in_a)
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for (auto p : c_patterns) {
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for (int i = 0; i < SIZE(sig_s); i++)
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p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
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if (sort_check_pattern(p))
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activation_patterns_cache[cell].insert(p);
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}
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for (int idx : used_in_b_parts)
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for (auto p : c_patterns) {
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p.first.append_bit(sig_s[idx]), p.second.bits.push_back(RTLIL::State::S1);
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if (sort_check_pattern(p))
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activation_patterns_cache[cell].insert(p);
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}
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}
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else
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{
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// Not a mux: just copy the activation patterns
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for (auto &p : c_patterns)
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activation_patterns_cache[cell].insert(p);
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}
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}
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return activation_patterns_cache[cell];
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}
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RTLIL::SigSpec bits_from_activation_patterns(const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &activation_patterns)
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@ -281,6 +345,8 @@ struct ShareWorker
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ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
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config(config), design(design), module(module)
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{
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fwd_ct.setup_internals();
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cone_ct.setup_internals();
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cone_ct.cell_types.erase("$mul");
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cone_ct.cell_types.erase("$mod");
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@ -292,13 +358,15 @@ struct ShareWorker
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cone_ct.cell_types.erase("$sshr");
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modwalker.setup(design, module);
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find_terminal_bits();
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find_shareable_cells();
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if (shareable_cells.size() < 2)
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return;
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log("Found %d cells in module %s that may be considered for resource sharing.\n",
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int(shareable_cells.size()), log_id(module));
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SIZE(shareable_cells), log_id(module));
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while (!shareable_cells.empty())
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{
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@ -307,6 +375,16 @@ struct ShareWorker
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log(" Analyzing resource sharing options for %s:\n", log_id(cell));
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const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &cell_activation_patterns = find_cell_activation_patterns(cell);
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RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
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if (cell_activation_patterns.count(std::pair<RTLIL::SigSpec, RTLIL::Const>())) {
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log (" Cell is always active. Therefore no sharing is possible.\n");
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continue;
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}
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log(" Found %d activation_patterns using ctrl signal %s.\n", SIZE(cell_activation_patterns), log_signal(cell_activation_signals));
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std::vector<RTLIL::Cell*> candidates;
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find_shareable_partners(candidates, cell);
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@ -315,19 +393,11 @@ struct ShareWorker
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continue;
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}
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log(" Found %d candidates:", int(candidates.size()));
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log(" Found %d candidates:", SIZE(candidates));
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for (auto c : candidates)
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log(" %s", log_id(c));
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log("\n");
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const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &cell_activation_patterns = find_cell_activation_patterns(cell);
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RTLIL::SigSpec cell_activation_signals = bits_from_activation_patterns(cell_activation_patterns);
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log(" Found %d activation_patterns using ctrl signal %s.\n", int(cell_activation_patterns.size()), log_signal(cell_activation_signals));
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if (cell_activation_patterns.empty())
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continue;
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for (auto other_cell : candidates)
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{
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log(" Analyzing resource sharing with %s:\n", log_id(other_cell));
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@ -335,11 +405,13 @@ struct ShareWorker
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const std::set<std::pair<RTLIL::SigSpec, RTLIL::Const>> &other_cell_activation_patterns = find_cell_activation_patterns(other_cell);
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RTLIL::SigSpec other_cell_activation_signals = bits_from_activation_patterns(other_cell_activation_patterns);
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log(" Found %d activation_patterns using ctrl signal %s.\n",
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int(other_cell_activation_patterns.size()), log_signal(other_cell_activation_signals));
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if (other_cell_activation_patterns.empty())
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if (other_cell_activation_patterns.count(std::pair<RTLIL::SigSpec, RTLIL::Const>())) {
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log (" Cell is always active. Therefore no sharing is possible.\n");
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continue;
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}
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log(" Found %d activation_patterns using ctrl signal %s.\n",
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SIZE(other_cell_activation_patterns), log_signal(other_cell_activation_signals));
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ezDefaultSAT ez;
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SatGen satgen(&ez, &modwalker.sigmap);
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@ -379,6 +451,7 @@ struct ShareWorker
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if (config.opt_fast && modwalker.cell_outputs[pbit.cell].size() >= 4)
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continue;
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// log(" Adding cell %s (%s) to SAT problem.\n", log_id(pbit.cell), log_id(pbit.cell->type));
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bits_queue.insert(modwalker.cell_inputs[pbit.cell].begin(), modwalker.cell_inputs[pbit.cell].end());
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satgen.importCell(pbit.cell);
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sat_cells.insert(pbit.cell);
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}
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@ -394,12 +467,12 @@ struct ShareWorker
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ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active)));
|
||||
|
||||
log(" Size of SAT problem: %d cells, %d variables, %d clauses\n",
|
||||
int(sat_cells.size()), ez.numCnfVariables(), ez.numCnfClauses());
|
||||
SIZE(sat_cells), ez.numCnfVariables(), ez.numCnfClauses());
|
||||
|
||||
if (ez.solve(sat_model, sat_model_values)) {
|
||||
log(" According to the SAT solver this pair of cells can not be shared.\n");
|
||||
log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), int(sat_model_values.size()));
|
||||
for (int i = int(sat_model_values.size())-1; i >= 0; i--)
|
||||
log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), SIZE(sat_model_values));
|
||||
for (int i = SIZE(sat_model_values)-1; i >= 0; i--)
|
||||
log("%c", sat_model_values[i] ? '1' : '0');
|
||||
log("\n");
|
||||
continue;
|
||||
|
|
@ -440,7 +513,7 @@ struct SharePass : public Pass {
|
|||
log(" for resource sharing.\n");
|
||||
log("\n");
|
||||
log(" -fast\n");
|
||||
log(" Only consider comparable primitive control logic in SAT solving, resulting\n");
|
||||
log(" Only consider the simple part of the control logic in SAT solving, resulting\n");
|
||||
log(" in much easier SAT problems at the cost of maybe missing some oportunities\n");
|
||||
log(" for resource sharing.\n");
|
||||
log("\n");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue