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Author SHA1 Message Date
Clifford Wolf 1f6737f08f Hotfix for yosysjs/demo03.html 2015-02-21 14:31:02 +01:00
Clifford Wolf 1fe15a5973 YosysJS: Wait for Viz to load 2015-02-21 14:25:34 +01:00
Clifford Wolf 4e6ca7760f Replaced ezDefaultSAT with ezSatPtr 2015-02-21 12:15:41 +01:00
Clifford Wolf f778a4081c Catch constants assigned to cell outputs in "flatten" 2015-02-21 11:21:28 +01:00
Clifford Wolf d5ce9a32ef Added deep recursion warning to AST simplify 2015-02-20 10:33:20 +01:00
Clifford Wolf dc1a0f06fc Parser support for complex delay expressions 2015-02-20 10:21:36 +01:00
Clifford Wolf 78b991d760 YosysJS firefox fixes 2015-02-19 13:55:36 +01:00
Clifford Wolf e0e6d130cd YosysJS stuff 2015-02-19 13:36:54 +01:00
Clifford Wolf 08c0fe164f format fixes in "sat -dump_json" 2015-02-19 13:19:04 +01:00
Clifford Wolf 1ecee6c49c Added "sat -dump_json" (WaveJSON format) 2015-02-19 10:53:40 +01:00
Clifford Wolf 20eb5cad4b Changed "show" defaults for Win32 2015-02-19 09:11:38 +01:00
Clifford Wolf c2ba4fb2fd Convert floating point cell parameters to strings 2015-02-18 23:35:23 +01:00
Clifford Wolf f41378af8c Fixed clang (svn trunk) warnings 2015-02-18 14:54:22 +01:00
Clifford Wolf e4cf604ffd Merge branch 'master' of github.com:cliffordwolf/yosys 2015-02-18 07:19:03 +01:00
Clifford Wolf 5f54be54b8 Added "select %xe %cie %coe" 2015-02-18 07:18:34 +01:00
Clifford Wolf 024aa559e2 wreduce help typo fix 2015-02-17 13:02:16 +01:00
Clifford Wolf 138547f41b CodingReadme 2015-02-17 13:01:01 +01:00
Clifford Wolf 4c22195c38 YosysJS fixes for firefox 2015-02-16 14:10:00 +01:00
Clifford Wolf 3e5e9a3889 More YosysJS stuff 2015-02-16 13:23:54 +01:00
Clifford Wolf 33e80b96c7 Added YosysJS wrapper 2015-02-16 12:41:48 +01:00
Clifford Wolf 0748ef638d Bugfix in wreduce 2015-02-16 09:08:00 +01:00
Clifford Wolf 162432a722 More yosys.js improvements 2015-02-16 00:11:22 +01:00
Clifford Wolf 0283703f9e Added Viz to yosys.js 2015-02-15 22:53:41 +01:00
Clifford Wolf 549d56bd21 Added yosys.js FS support 2015-02-15 18:10:54 +01:00
Clifford Wolf 8d45f81046 More emcc stuff 2015-02-15 17:15:29 +01:00
Clifford Wolf c2cc342e1a Improved yosys.js example 2015-02-15 16:16:08 +01:00
Clifford Wolf 4d34d031f9 Added "stat" to "synth" and "synth_xilinx" 2015-02-15 13:25:15 +01:00
Clifford Wolf 881dcd8af9 Added final checks to "synth" and "synth_xilinx" 2015-02-15 13:00:00 +01:00
Clifford Wolf 40f021e136 Added "check -noinit" 2015-02-15 12:58:12 +01:00
Clifford Wolf a54c994e2b Cosmetic fixes in "hierarchy" for blackbox modules 2015-02-15 12:57:41 +01:00
Clifford Wolf 3216f9420e More emscripten stuff, Added example app 2015-02-15 12:09:30 +01:00
Clifford Wolf 86819cc9f8 Fixed default EMCCFLAGS 2015-02-15 10:30:29 +01:00
Clifford Wolf ec05242c27 Smaller default parameters in $mem simlib model 2015-02-15 00:20:05 +01:00
Clifford Wolf c6ae9ebb79 Fixed "stat" handling of blackbox modules 2015-02-14 22:36:34 +01:00
Clifford Wolf e9368a1d7e Various fixes for memories with offsets 2015-02-14 14:21:15 +01:00
Clifford Wolf dcf2e24240 Added $meminit support to "memory" command 2015-02-14 12:55:03 +01:00
Clifford Wolf 913c304fe6 Added $meminit test case 2015-02-14 11:26:20 +01:00
Clifford Wolf 7f1a1759d7 Added "read_verilog -nomeminit" and "nomeminit" attribute 2015-02-14 11:21:12 +01:00
Clifford Wolf a8e9d37c14 Creating $meminit cells in verilog front-end 2015-02-14 10:49:30 +01:00
Clifford Wolf 910556560f Added $meminit cell type 2015-02-14 10:23:03 +01:00
Clifford Wolf ef151b0b30 Fixed handling of "//" in filenames in verilog pre-processor 2015-02-14 08:41:03 +01:00
Clifford Wolf 756b4064b2 Fixed "write_verilog -attr2comment" handling of "*/" in strings 2015-02-13 22:48:10 +01:00
Clifford Wolf a0a0594d1e hotfix in "check" command 2015-02-13 14:40:49 +01:00
Clifford Wolf 04cb947d6a Added "check" command 2015-02-13 14:34:51 +01:00
Clifford Wolf cd919abdf1 Added AstNode::simplify() recursion counter 2015-02-13 12:33:12 +01:00
Clifford Wolf 2f0edff019 Added EMCCFLAGS 2015-02-13 12:32:04 +01:00
Clifford Wolf d58c3eca3a Some test related fixes 
(incl. removal of three bad test cases)
 2015-02-12 17:45:44 +01:00
Clifford Wolf 554a8df5e2 Added "proc_dlatch" 2015-02-12 16:56:01 +01:00
Clifford Wolf 87819c62fa Less aggressive "share" defaults 2015-02-10 20:51:37 +01:00
Clifford Wolf 4f68a77e3f Improved read_verilog support for empty behavioral statements 2015-02-10 12:17:29 +01:00