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Code Activity
14787 commits 122 branches 59 tags 43 MiB
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678 commits

Author SHA1 Message Date
Claire Xenia Wolf
6d56d4ecfc Merge branch 'master' of github.com:YosysHQ/yosys into claire/eqystuff 2023-01-11 04:10:12 +01:00
Peter Gadfort
58cca9592d stat: ensure area is included in json output 
Signed-off-by: Peter Gadfort <peter.gadfort@gmail.com>
 2022-12-29 21:51:46 -05:00
Jannis Harder
4a0ed35aab xprop: Improve signal splitting code 
Avoid splitting output ports twice when combining -split-outputs with
-split-public and clean up the corresponding code.
 2022-12-12 17:51:01 +01:00
Claire Xenia Wolf
6a6e1d8424 Improvements in "viz" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-09 18:28:17 +01:00
Claire Xenia Wolf
3454bddbe2 Merge branch 'claire/eqystuff' of github.com:YosysHQ/yosys into claire/eqystuff 2022-12-08 20:06:23 +01:00
Jannis Harder
172a8e79f0 xprop: Add -split-public option 2022-12-08 20:00:01 +01:00
Claire Xenia Wolf
068031d2aa Improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-07 16:10:58 +01:00
Claire Xenia Wolf
aeba966475 Improvements in "viz" pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-07 12:46:49 +01:00
Claire Xenia Wolf
c679b408cb Various improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-06 16:43:01 +01:00
Claire Xenia Wolf
2895a66784 Bugfix in splitcells pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-06 16:00:48 +01:00
Claire Xenia Wolf
e151e44caa Improvements in "viz" command 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 19:32:31 +01:00
Claire Xenia Wolf
c9f4b06cb2 Add "viz" pass for visualizing big-picture data flow in larger designs 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 11:35:10 +01:00
Claire Xenia Wolf
92fc6cd4a9 Add splitcells pass 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2022-12-04 01:33:04 +01:00
Jannis Harder
7036a312bf stat: Fix JSON output for empty designs 2022-12-02 14:36:19 +01:00
Jannis Harder
ed02d52f30 tee: Allow logging command output to a given scratchpad value 2022-12-02 14:36:19 +01:00
Jannis Harder
ce708122a5 New xprop pass to encode 3-valued x-propagation using 2-valued logic 2022-11-30 19:01:28 +01:00
KrystalDelusion
a14dec79eb
Rst docs conversion (#3496) 
Rst docs conversion
 2022-11-15 12:55:22 +01:00
Kamyar Mohajerani
69787f1906 remove extra space in formating 2022-09-22 15:46:36 +01:00
Kamyar Mohajerani
bc1e579483 stat: add tech tech-specific utilizations to json 
- refactor resource util. estimation/calculations for Xilinx and CMOS
 - don't print log_header if "-json" is set
 2022-09-22 15:46:36 +01:00
N. Engelhardt
7d35003c16
Merge pull request #3449 from YosysHQ/aki/show_pathrw 2022-08-25 17:06:29 +02:00
KrystalDelusion
9465b2af95 Fitting help messages to 80 character width 
Uses the regex below to search (using vscode):
	^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\);

Finds any log messages double indented (which help messages are)
and checks if *either* there are is no newline character at the end,
*or* the number of characters before the newline is more than 80.
 2022-08-24 10:40:57 +12:00
Aki Van Ness
1433a63165
yosys: passes: cmds: show: added filename re-writing to show -lib 2022-08-22 06:04:54 -04:00
Jannis Harder
65145db7e7 rename: Add -witness mode 2022-08-16 13:37:30 +02:00
Jannis Harder
0cdb14df41 setundef: Do not add anyseq / anyconst to unused memory port clocks 
Instead set those unused clocks to zero.
 2022-08-16 13:37:30 +02:00
Jannis Harder
c0063288d6 Add the $anyinit cell and the formalff pass 
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
 2022-08-16 13:37:30 +02:00
N. Engelhardt
6f439dc59a
Merge pull request #3425 from YosysHQ/lofty/stat-json 2022-08-11 17:00:54 +02:00
Lofty
59facfa98c stat: add option for machine-readable json output 2022-08-11 13:41:01 +01:00
Lofty
a48dcd1d40 rename: add -scramble-name option to randomly rename selections 2022-08-08 16:03:28 +01:00
George Rennie
5dfad5101d chformal: Rename -coverprecond to -coverenable 2022-06-18 18:28:12 +01:00
Jannis Harder
e39c422734 chformal: Test -coverprecond and reuse the src attribute 2022-06-18 18:19:26 +01:00
George Rennie
c659bd1878 chformal: Add -coverprecond option 
This inserts $cover cells to cover the enable signal (precondition)
for the selected formal cells.
 2022-06-18 18:19:26 +01:00
N. Engelhardt
3eaa9e38e0
Merge pull request #3196 from bfg86/bfg86/rename 
Add -suffix option to rename -wire
 2022-06-13 16:00:04 +02:00
bfg86
aedd3b7999 Updating help-text with nakengelhardts suggestion. 2022-06-13 09:35:10 +02:00
N. Engelhardt
b8ede6162b
Merge pull request #3349 from nakengelhardt/select_count_scratchpad 
Make 'stat' and 'select -count' save counts to scratchpad
 2022-06-09 17:15:02 +02:00
Lofty
aae2c01326 sta: warn on unrecognised cells only once 2022-06-08 09:31:49 +01:00
Miodrag Milanovic
d88a5d26b7 Fix preventing show crashing with newer graphviz 2022-06-03 08:38:16 +02:00
N. Engelhardt
61b05051e1 also make 'stat' save counts to scratchpad 2022-06-01 16:01:07 +02:00
N. Engelhardt
a55c3db384 have 'select -count' save the count to scratchpad entry 'select.count' 2022-06-01 14:39:33 +02:00
Jannis Harder
fc65ea47df select: Fix -assert-none and -assert-any error output and docs 
Both of these options consider a selection containing only empty modules
as non-empty. This wasn't mentioned in the documentation nor did the
error message when using `select -assert-none` list those empty modules,
which produced a very confusing error message complaining about a
non-empty selection followed by an empty listing of the selection.

This fixes the documentation and changes the `-assert-none` and
`-assert-any` assertion error messages to also output fully selected
modules (this includes selected empty modules).

It doesn't change the messages for `-assert-count` etc. as they don't
count modules.
 2022-05-19 14:07:34 +02:00
Marcelina Kościelnicka
0aec79a0da show: Fix width labels. 
See #3266.
 2022-04-04 22:48:09 +02:00
Claire Xen
e016518866
Merge pull request #2019 from boqwxp/glift 
Add `glift` command for creating gate-level information flow tracking models and optimization problems
 2022-02-11 15:51:24 +01:00
bfg86
7ac98d1c87 Add -suffix option to rename -wire. 
See #3195
 2022-02-11 00:05:13 +01:00
Marcelina Kościelnicka
93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Catherine
4f1d62d9b2 bugpoint: avoid infinite loop between -connections and -wires. 
Fixes #3113.
 2021-12-15 08:17:02 +00:00
Marcelina Kościelnicka
0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. 
This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
 2021-12-12 19:56:50 +01:00
Lofty
77327b2544 sta: very crude static timing analysis pass 
Co-authored-by: Eddie Hung <eddie@fpgeh.com>
 2021-11-25 17:20:27 +01:00
Marcelina Kościelnicka
107aad2cd2 show: Fix wire bit indexing. 
Fixes #3078.
 2021-11-12 15:09:58 +01:00
Marcelina Kościelnicka
e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka
c58ac63c97 logger: Add -check-expected subcommand. 
This allows us to have multiple "expect this warning" calls in a single
long script, covering only as many passes as necessary.
 2021-08-12 17:41:39 +02:00
Marcelina Kościelnicka
fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00