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Author	SHA1	Message	Date
Clifford Wolf	1dcb683fcb	Write yosys version to output files	2013-11-03 21:41:39 +01:00
Clifford Wolf	eab536a203	Merge branch 'master' of github.com:cliffordwolf/yosys	2013-11-03 21:13:21 +01:00
Clifford Wolf	d2b083f5cb	Fixed detectSignWidthWorker (ast frontend) for AST_CONCAT	2013-11-03 18:56:45 +01:00
Clifford Wolf	f7f0af6f9c	Added resolution of positional arguments to hierarchy pass	2013-11-03 09:42:51 +01:00
Clifford Wolf	4a60e5842d	Ignore explicit unconnected ports in intersynth backend	2013-11-03 09:00:51 +01:00
Clifford Wolf	ada80545fa	Behavior should be identical now to rev. 0b4a64ac6a (next: testing before constfold fixes)	2013-11-02 21:13:01 +01:00
Clifford Wolf	f912e029de	Added roadmap to readme file	2013-11-02 13:19:04 +01:00
Clifford Wolf	943329c1dc	Various ast changes for early expression width detection (prep for constfold fixes)	2013-11-02 13:00:17 +01:00
Clifford Wolf	0b4a64ac6a	Added DFFSR cell to techlibs/cmos/cmos_cells.lib	2013-10-31 12:27:35 +01:00
Clifford Wolf	0efe16f118	Added placeholder check to dfflibmap and cleaned up some other placeholder checks	2013-10-31 12:27:07 +01:00
Clifford Wolf	961eaa0077	Changed MiniSAT feater defines again	2013-10-31 12:02:18 +01:00
Clifford Wolf	d78a9dfb37	Added paragraph to README file to avoid mycells.lib confusion	2013-10-31 11:15:00 +01:00
Clifford Wolf	f024b19ed9	README file typo fix	2013-10-31 01:15:07 +01:00
Clifford Wolf	cc7986a3e5	Some additions to the README file	2013-10-31 01:09:24 +01:00
Clifford Wolf	3fc6c9aac6	Fixed ezminisat C++ errors: undef PRIi64	2013-10-30 17:25:39 +01:00
Clifford Wolf	b8bfa020fa	Added detection for endless recursion in fsm_detect pass	2013-10-30 00:47:58 +01:00
Clifford Wolf	888c43210b	Fixed help message typo (memory pass)	2013-10-30 00:47:31 +01:00
Clifford Wolf	613750155d	Added -format option to splitnets	2013-10-29 11:01:04 +01:00
Clifford Wolf	6bfeb17f05	Merge pull request #12 from jameswalmsley/master ... [EXAMPLES] Ported the mojo counter example to Zynq ZED board.	2013-10-27 14:35:15 -07:00
James Walmsley	40b3551b45	[EXAMPLES] Ported the mojo counter example to Zynq ZED board. ... Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.	2013-10-27 21:48:39 +01:00
Clifford Wolf	f39c0c9928	Fixed get_share_file_name() for installed yosys	2013-10-27 10:05:19 +01:00
Clifford Wolf	88cd2eadf5	Cleanups in xilinx examples	2013-10-27 09:58:53 +01:00
Clifford Wolf	4a3669d871	Added synth_xilinx command	2013-10-27 09:51:06 +01:00
Clifford Wolf	73e68fe323	Added API and Makefile rules for share/ files	2013-10-27 09:33:26 +01:00
Clifford Wolf	bd2c8ec886	Added design->full_selection() helper method	2013-10-27 09:30:58 +01:00
Clifford Wolf	90b016716b	Moved simple xilinx counter sim example to subdir	2013-10-27 09:30:17 +01:00
Clifford Wolf	02f321b6fc	Xilinx mojo_counter example is now working	2013-10-27 08:21:56 +01:00
Clifford Wolf	d9fa1e5a1d	Fixed hex string generation bug in edif backend	2013-10-27 08:21:05 +01:00
Clifford Wolf	d635f8adaa	Renamed techlibs/xilinx7 to techlibs/xilinx	2013-10-26 22:29:40 +02:00
Clifford Wolf	4007b41d40	Improved xilinx mojo_counter example	2013-10-26 22:28:42 +02:00
Clifford Wolf	ceb971eab9	Added support for i/o buffers to iopadmap	2013-10-26 22:27:40 +02:00
Clifford Wolf	b934a2d209	Added another xilinx example (not funcional yet)	2013-10-26 17:22:29 +02:00
Clifford Wolf	dd56004fc0	Added support for sr flip-flops to dfflibmap	2013-10-24 18:20:06 +02:00
Clifford Wolf	628b994cf6	Added support for complex set-reset flip-flops in proc_dff	2013-10-24 16:54:05 +02:00
Clifford Wolf	e679a5d046	Fixed handling of boolean attributes (passes)	2013-10-24 11:37:54 +02:00
Clifford Wolf	e9dede01ca	Fixed handling of boolean attributes (backends)	2013-10-24 11:27:30 +02:00
Clifford Wolf	23cf23418c	Fixed handling of boolean attributes (frontends)	2013-10-24 11:20:13 +02:00
Clifford Wolf	eae43e2db4	Fixed handling of boolean attributes (kernel)	2013-10-24 10:59:27 +02:00
Clifford Wolf	77726fb5fe	Fixed parsing of value-less attributes in ilang	2013-10-23 18:38:31 +02:00
Clifford Wolf	d61699843f	Improved handling of dff with async resets	2013-10-21 14:51:58 +02:00
Clifford Wolf	56ea230676	Added handling of multiple async paths in proc_arst	2013-10-19 00:50:13 +02:00
Clifford Wolf	8e8f1994b8	Changed NEW_WIRE API to return the wire, not the signal	2013-10-18 14:19:45 +02:00
Clifford Wolf	bfa1a65fa9	Added dffsr support to proc_dff pass	2013-10-18 13:26:52 +02:00
Clifford Wolf	cc5e379eca	Added RTLIL NEW_WIRE macro	2013-10-18 13:25:24 +02:00
Clifford Wolf	0836a1f2ba	Bugfix in dffsr techmap rules	2013-10-18 13:24:44 +02:00
Clifford Wolf	8197169f8d	Added techmap rules for $sr, $dffsr and $dlatch	2013-10-18 12:29:21 +02:00
Clifford Wolf	e0f693cbb0	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	2013-10-18 12:13:34 +02:00
Clifford Wolf	5998c101a4	Added $sr, $dffsr and $dlatch cell types	2013-10-18 11:56:16 +02:00
Clifford Wolf	9bc703b964	Improved way of connecting ports in techmap pass	2013-10-17 22:19:38 +02:00
Clifford Wolf	8cc53ef72c	Only prefer connected signals iff they have public names	2013-10-17 22:10:55 +02:00