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Author	SHA1	Message	Date
Clifford Wolf	1b3a60976d	Using RTLIL::id2cstr for prompt printing	2013-11-29 11:55:18 +01:00
Clifford Wolf	ed441346ca	Added dump -m and -n options	2013-11-29 10:33:36 +01:00
Clifford Wolf	f89ecbc100	Progress on AppNote 011	2013-11-28 23:09:03 +01:00
Clifford Wolf	d90ef1e143	Merge pull request #17 from mschmoelzer/master ... Include unistd.h in svgview.cpp (required for getcwd() function)	2013-11-28 13:04:45 -08:00
Clifford Wolf	10aa08dca1	Fixed temp net name generation in rtlil process generator for abbreviated name matching	2013-11-28 21:47:08 +01:00
Clifford Wolf	c60aaf8fa3	Added pattern support to "ls" command	2013-11-28 21:34:41 +01:00
Clifford Wolf	293356e87c	Improved ID matching scheme in select (and thus for all commands)	2013-11-28 21:13:16 +01:00
Clifford Wolf	792bbad448	Fixes and improvements in "show" command	2013-11-28 21:02:19 +01:00
Martin Schmölzer	6ad868ae25	Include unistd.h in svgview.cpp (required for getcwd() function) ... This fixes compilation on Arch Linux, which otherwise fails. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>	2013-11-28 18:43:33 +01:00
Clifford Wolf	9595eca181	More progress on AppNote 011	2013-11-28 17:39:16 +01:00
Clifford Wolf	0e52f3fa01	Added "src" attribute to processes	2013-11-28 17:37:50 +01:00
Clifford Wolf	6dfb66d262	Started writing appnote 011	2013-11-28 13:48:38 +01:00
Clifford Wolf	5af7f4db72	Added support for "show -pause" and "show -format dot"	2013-11-28 13:35:28 +01:00
Clifford Wolf	143a58bccc	Added QGraphicsWebView to yosys-svgviewer	2013-11-28 11:57:25 +01:00
Clifford Wolf	1268182f0b	Updated ABC to 9241719523f6	2013-11-28 00:43:17 +01:00
Clifford Wolf	9826f6ae02	Added some svgviewer code for possible future switch to QGraphicsWebView	2013-11-27 20:43:42 +01:00
Clifford Wolf	18e52d81bf	Merge branch 'master' of github.com:cliffordwolf/yosys	2013-11-27 09:08:42 +01:00
Clifford Wolf	38e7fa6530	Tighter integration of ABC build	2013-11-27 09:08:35 +01:00
Clifford Wolf	0256105ac2	Set version number to 0.1.0+	2013-11-27 06:29:13 +01:00
Clifford Wolf	bc3cc88719	Started implementing undef support in "sat" command	2013-11-25 21:40:00 +01:00
Clifford Wolf	3d95047ce2	Bugfixes in new "stat" command	2013-11-25 21:08:34 +01:00
Clifford Wolf	4c7d6e63ec	Added "stat" command	2013-11-25 20:43:57 +01:00
Clifford Wolf	61412d167f	Improvements in satgen undef handling	2013-11-25 16:50:45 +01:00
Clifford Wolf	bd65e67d8a	Improvements in satgen undef handling	2013-11-25 15:12:01 +01:00
Clifford Wolf	11e8118589	Added ezsat vec_const() api	2013-11-25 15:10:32 +01:00
Clifford Wolf	8c3f4b3957	Started implementing undef handling in satgen	2013-11-25 04:51:33 +01:00
Clifford Wolf	4d43331748	Removed undef feature from ezsat api	2013-11-25 02:50:34 +01:00
Clifford Wolf	76f7c10cfc	Using simplemap mappers from techmap	2013-11-24 23:31:14 +01:00
Clifford Wolf	3ee33cbdaf	Added simplemap pass	2013-11-24 22:52:30 +01:00
Clifford Wolf	1afe6589df	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	2013-11-24 20:44:00 +01:00
Clifford Wolf	8dafecd34d	Added module->avail_parameters (for advanced techmap features)	2013-11-24 20:29:07 +01:00
Clifford Wolf	4011d47646	Added techmap -D and -I options	2013-11-24 20:04:48 +01:00
Clifford Wolf	7d9a90396d	Added verilog frontend -ignore_redef option	2013-11-24 19:57:42 +01:00
Clifford Wolf	20175afd29	Added "techmap -share_map" option	2013-11-24 19:50:25 +01:00
Clifford Wolf	019b301541	Early wire/reg/parameter width calculation in ast/simplify	2013-11-24 19:40:23 +01:00
Clifford Wolf	620b7c900a	Updated TODOs	2013-11-24 17:58:05 +01:00
Clifford Wolf	ae798d3fd5	Fixed xilinx/example_sim_counter test bench	2013-11-24 17:55:46 +01:00
Clifford Wolf	41205afc39	Added proper dumping of signed/unsigned parameters to verilog backend	2013-11-24 17:47:22 +01:00
Clifford Wolf	0ef22c7609	Added support for signed parameters in ilang	2013-11-24 17:37:27 +01:00
Clifford Wolf	7eaad2218d	Removed now obsolete test cases	2013-11-24 17:30:04 +01:00
Clifford Wolf	f71e27dbf1	Remove auto_wire framework (smarter than the verilog standard)	2013-11-24 17:29:11 +01:00
Clifford Wolf	609caa23b5	Implemented correct handling of signed module parameters	2013-11-24 17:17:21 +01:00
Clifford Wolf	1e6836933d	Added modelsim support to autotest	2013-11-24 15:10:43 +01:00
Clifford Wolf	72b35e0b99	Fixed "flatten" top-module detection: Only use on fully selected designs	2013-11-24 14:10:46 +01:00
Clifford Wolf	981677cf09	Fixed "make install" dependencies	2013-11-24 05:05:50 +01:00
Clifford Wolf	28093d9dd2	Added "top" attribute to mark top module in hierarchy	2013-11-24 05:03:43 +01:00
Clifford Wolf	a4edecb0ca	Updated command-reference-manual.tex	2013-11-23 20:09:47 +01:00
Clifford Wolf	db8ce0fe95	AppNote 010 typo fixes and corrections	2013-11-23 20:04:51 +01:00
Clifford Wolf	e216e0e291	AppNote 010 progress	2013-11-23 18:52:41 +01:00
Clifford Wolf	5f9c7fc6ea	Improved handling of techmap special wires	2013-11-23 16:49:58 +01:00