3880 commits

Author	SHA1	Message	Date
Clifford Wolf	91704a7853	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys ... (see https://github.com/cliffordwolf/yosys/pull/28)	2014-03-11 14:24:24 +01:00
Clifford Wolf	fa75c8286e	Fixed memory corruption in passes/abc/blifparse.cc	2014-03-11 13:09:01 +01:00
Clifford Wolf	fcae92868d	Fixed dumping of timing() { .. } block in libparse	2014-03-09 15:16:07 +01:00
Clifford Wolf	22aabe05c9	Verbose reading of liberty and constr files in ABC pass	2014-03-09 15:15:38 +01:00
Clifford Wolf	e3b11ea2d6	Fixed bug in freduce command	2014-03-07 18:44:23 +01:00
Clifford Wolf	6f8865d81a	Some minor code cleanups in freduce command	2014-03-07 18:29:04 +01:00
Clifford Wolf	54d74cf616	Added freduce -dump	2014-03-06 22:06:58 +01:00
Clifford Wolf	da5859a674	Added freduce -stop	2014-03-06 18:14:26 +01:00
Clifford Wolf	9b9c3327cc	Fixed undef handling in opt_reduce	2014-03-06 14:18:34 +01:00
Clifford Wolf	1ecaf1bb76	Added techmap -max_iter option	2014-03-06 12:15:17 +01:00
Clifford Wolf	96e753041d	fixed freduce for Minisat::SimpSolver: use frozen_literal()	2014-03-03 02:14:27 +01:00
Clifford Wolf	9e99984336	Fixed const folding of $bu0 cells	2014-02-27 04:09:32 +01:00
Clifford Wolf	548519875b	Fixed bug (typo) in passes/opt/opt_const.cc	2014-02-22 17:07:22 +01:00
Clifford Wolf	8b508dc90b	Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst	2014-02-21 23:34:45 +01:00
Clifford Wolf	4e43cb7317	Added _TECHMAP_REPLACE_ feature to techmap	2014-02-20 23:42:07 +01:00
Clifford Wolf	737b71c735	Added "extract -ignore_parameters" and "extract -ignore_param ..."	2014-02-20 23:31:13 +01:00
Clifford Wolf	236fc4209c	Added "extract -map %<design_name>"	2014-02-20 23:30:15 +01:00
Clifford Wolf	483c99fe46	Added "design -push" and "design -pop"	2014-02-20 23:28:59 +01:00
Clifford Wolf	0dadfed46d	Added connwrappers command	2014-02-20 20:44:11 +01:00
Clifford Wolf	23a3b488a0	Merge branch 'master' of github.com:cliffordwolf/yosys	2014-02-18 20:05:53 +01:00
Clifford Wolf	a71d09421d	Added techmap support for _TECHMAP_CONNMAP_*_	2014-02-18 19:51:00 +01:00
Clifford Wolf	a78bba1f5c	Added "sat -dump_cnf"	2014-02-18 09:29:08 +01:00
Clifford Wolf	32af10fa9b	Coding style corrections in SatHelper::dump_model_to_vcd()	2014-02-18 09:28:05 +01:00
Clifford Wolf	13051e6acf	Added "sat -initsteps"	2014-02-18 09:03:16 +01:00
Clifford Wolf	0851c2b6ea	Renamed "sat -dump_fail_to_vcd" to "sat -dump_vcd" and some minor cleanups	2014-02-17 13:59:39 +01:00
Andrew Zonenberg	4a948d780a	Added "-dump_fail_to_vcd" argument to SAT solver	2014-02-17 13:52:36 +01:00
Clifford Wolf	ca53ef5098	Better preserve wires when flattening (in comparison to techmap)	2014-02-17 09:44:39 +01:00
Clifford Wolf	6d63f39eb6	Added some additional checks to techmap	2014-02-16 22:18:06 +01:00
Clifford Wolf	a9b11d7c83	Added CONSTMSK and CONSTVAL feature to techmap	2014-02-16 21:58:59 +01:00
Clifford Wolf	28e14ee50a	Fixed handling of "keep" attribute on wires in opt_clean	2014-02-16 21:58:27 +01:00
Clifford Wolf	42ce3db983	Fixed use of selection in splitnets command	2014-02-16 17:39:50 +01:00
Clifford Wolf	d3dc22a90f	Added recursion support to techmap	2014-02-16 17:16:44 +01:00
Clifford Wolf	9a816b65a8	Added != support for relational select pattern	2014-02-16 00:16:54 +01:00
Clifford Wolf	623a68f528	Added iopadmap -bits	2014-02-15 21:59:26 +01:00
Clifford Wolf	cdf0f10760	Fixed dfflibmap for cell libraries with no set-reset-ff	2014-02-15 16:34:12 +01:00
Clifford Wolf	67effc9f5b	Fixed opt_const handling of double invert with non-1 output width	2014-02-15 13:16:08 +01:00
Clifford Wolf	3121d19d95	Added abc -keepff option	2014-02-14 11:28:42 +01:00
Clifford Wolf	de3ea9269a	updated default ABC command strings	2014-02-13 19:14:15 +01:00
Clifford Wolf	a123941618	Updated ABC	2014-02-13 18:56:36 +01:00
Clifford Wolf	cd9e8741a7	Implemented read_verilog -defer	2014-02-13 13:59:13 +01:00
Clifford Wolf	b463907890	Removed double blanks in ABC default command sequences	2014-02-13 08:12:52 +01:00
Clifford Wolf	7664f5d92b	Updated ABC and some related changes	2014-02-13 08:07:08 +01:00
Clifford Wolf	ab71bd0746	Updated ABC to rev e97a6e1d59b9	2014-02-12 08:35:42 +01:00
Clifford Wolf	38469e7686	Various improvements in expose command (added -sep and -cut)	2014-02-09 11:07:46 +01:00
Clifford Wolf	b6f33576d5	Added delete {-input|-output|-port}	2014-02-09 10:03:26 +01:00
Clifford Wolf	b3b5fac191	Bugfix in delete command	2014-02-09 09:34:58 +01:00
Clifford Wolf	85914c36e5	Fixed handling of async reset in expose -evert-dff	2014-02-08 21:26:40 +01:00
Clifford Wolf	db86aaa07d	Build fixes for log cmd	2014-02-08 21:21:51 +01:00
Clifford Wolf	c06de50f05	Merge branch 'master' of github.com:cliffordwolf/yosys	2014-02-08 21:08:46 +01:00
Clifford Wolf	0935e20003	Implemented expose -evert-dff	2014-02-08 21:08:38 +01:00