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Code
Activity
a9b11d7c83
yosys
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passes
History
Clifford Wolf
a9b11d7c83
Added CONSTMSK and CONSTVAL feature to techmap
2014-02-16 21:58:59 +01:00
..
abc
Added abc -keepff option
2014-02-14 11:28:42 +01:00
cmds
Fixed use of selection in splitnets command
2014-02-16 17:39:50 +01:00
fsm
Fixes in fsm detect/extract for better detection of non-fsm circuits
2013-12-06 12:53:20 +01:00
hierarchy
Implemented read_verilog -defer
2014-02-13 13:59:13 +01:00
memory
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
2014-02-08 19:13:19 +01:00
opt
Fixed handling of "keep" attribute on wires in opt_clean
2014-02-16 21:58:27 +01:00
proc
Tiny cleanup in proc_mux.cc
2014-01-03 16:54:59 +01:00
sat
Various improvements in expose command (added -sep and -cut)
2014-02-09 11:07:46 +01:00
techmap
Added CONSTMSK and CONSTVAL feature to techmap
2014-02-16 21:58:59 +01:00