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14709 commits

Author SHA1 Message Date
Krystine Sherwin
37573a6f00
Docs: Use json for cellref
e.g.
```
.. autocell:: $alu
   :source:
   :linenos:
```
2024-10-15 07:26:04 +13:00
Krystine Sherwin
9533cf2916
Makefile: Use dump-cells-json for docs 2024-10-15 07:26:03 +13:00
Krystine Sherwin
a119d41303
Docs: Move appendix toc to main toc
Adds an Appendix header to sidebar toc instead of being an (empty) subpage.
2024-10-15 07:25:27 +13:00
Krystine Sherwin
7c5b10fe50
cellref: Add json dump
New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).
2024-10-15 07:25:27 +13:00
Krystine Sherwin
7eb33f1933
Docs: Testing autocell 2024-10-15 07:24:14 +13:00
Krystine Sherwin
84f2968031
cellref: Better name checking
Fix RTD not including source with warning
`WARNING: invalid signature for autocellsource ('/home/docs/checkouts/readthedocs.org/user_builds/yosys/checkouts/manual-rewrite/source/generated/simlib.v:$alu::__source')`.
2024-10-15 07:24:14 +13:00
Krystine Sherwin
ccd3bace23
Docs: Add cells loc config value 2024-10-15 07:24:14 +13:00
Krystine Sherwin
1b0d8633c4
Docs: Add root to ToC 2024-10-15 07:24:14 +13:00
Krystine Sherwin
a66e94c5da
Docs: Switch to furo-ys 2024-10-15 07:24:14 +13:00
Krystine Sherwin
e5f54dd7cd
Docs: Cell reference as a custom documenter
Use autodocs to perform cell reference docs generation instead of generating rst files directly.
e.g.
```
.. autocell:: simlib.v:$alu
   :source:
   :linenos:
```
2024-10-15 07:23:45 +13:00
Krystine Sherwin
06e5e18371
simlib.v: Autolink referenced cells in alu 2024-10-15 07:23:45 +13:00
Krystine Sherwin
063a6bc2d7
register.cc: Include properties in docs 2024-10-15 07:23:45 +13:00
Krystine Sherwin
4c9c4c1419
celltypes.h: Add extra properties 2024-10-15 07:23:45 +13:00
Krystine Sherwin
21747c468c
Docs: Improve cell_help usage
- Drop `cell_code` and instead map code lookups to the `cell_help` dict.
- Add helper functions to struct for checking and getting the right cell.
- Add `CellType` for cell to `write_cell_rst` function declaration in
  preparation for use in future.
- Iterate over `yosys_celltypes.cell_types` when exporting cell rst files,
  reporting errors for any cells defined in `cell_types` but not
  `cell_help_messages`.
2024-10-15 07:23:45 +13:00
Krystine Sherwin
40ba92e956
Docs: Reflow line length 2024-10-15 07:23:45 +13:00
Akash Levy
94b4ccffcd Bump yosys-slang dep 2024-10-14 11:23:30 -07:00
Krystine Sherwin
829e02ec5b
Docs: Shorten cmd:ref 2024-10-15 07:22:04 +13:00
Akash Levy
469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Krystine Sherwin
e4ec3717bc
Docs: Update internal cells to autoref 2024-10-15 07:18:28 +13:00
Krystine Sherwin
c0f9828b3c
Docs: Add autoref role
Use new `autoref` role when using single backticks. Allows automatic mapping to a cmd ref or a cell ref.
2024-10-15 07:17:36 +13:00
Krystine Sherwin
f9b4e04fef
Docs: Add cell reference
Subclass the command reference code in order to support smart references to the internal cells.
2024-10-15 07:17:36 +13:00
Krystine Sherwin
c98d134662
cellhelp: Extra newline
Fix `$macc` page.
2024-10-15 07:17:35 +13:00
Krystine Sherwin
d629aa6bf1
cellhelp: Split gate-level and word-level cells 2024-10-15 07:17:35 +13:00
Krystine Sherwin
1a4ada40fe
Docs: Add cell gen to makefile
Generate in a temp directory and use `rsync -rc` to only update rst files that have changed.  This prevents sphinx from having to re-generate every cmd/cell page any time the git sha changes.
Also change cmd gen to match.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
57cd8d29db
cellhelp: Add default format parse for simcells
Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst.
Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
a2b2904ed8
cellhelp: Add source line to help
Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
784292626e
cellhelp: Rename short_desc to title 2024-10-15 07:16:39 +13:00
Krystine Sherwin
1e5a50ff3a
Docs: Convert write_cell_rst to use SimHelper 2024-10-15 07:16:39 +13:00
Krystine Sherwin
4662476ec8
Docs: Test $alu with v2 help format 2024-10-15 07:16:39 +13:00
Krystine Sherwin
600149a824
Docs: Add back message for empty help 2024-10-15 07:16:39 +13:00
Krystine Sherwin
6bbe763845
Docs: Put cell library help strings into a struct
Allows for more expressive code when constructing help messages for cells.
Will also move extra logic in parsing help strings into the initial python parse instead of doing it in the C++ at export time.
2024-10-15 07:16:39 +13:00
Krystine Sherwin
a6641da73c
Docs: Initial version of cell_ref autogen 2024-10-15 07:16:39 +13:00
Akash Levy
0d5aa5bb77 Update Makefile to include sat 2024-10-14 09:57:56 -07:00
Emil J
1113b88cb2
Merge pull request #4649 from YosysHQ/emil/synth-xilinx-json
synth_xilinx: add -json
2024-10-14 06:45:14 -07:00
Emil J
caf56ca3e8
Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip
Represent string constants as strings
2024-10-14 06:42:54 -07:00
N. Engelhardt
518b6aec36
Merge pull request #4654 from YosysHQ/micko/vhdl_assert 2024-10-14 15:05:22 +02:00
Emil J. Tywoniak
bc5d9d1bd3 functional: fix std::move usage in Factory::constant 2024-10-14 06:28:14 +02:00
Emil J. Tywoniak
785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Akash Levy
f4de53120e Bump dep 2024-10-13 11:01:54 -07:00
Akash Levy
8e6ac65dd8
Merge branch 'YosysHQ:main' into main 2024-10-13 10:59:19 -07:00
Emil J
61ed9b6263
Merge pull request #4608 from phsauter/rtlil-const-compress
rtlil: add Const::compress helper function
2024-10-12 20:38:25 -07:00
github-actions[bot]
7f2bf3170f Bump version 2024-10-13 00:22:25 +00:00
Jean-François Nguyen
f953a516d0 cxxrtl: fix handling of 0-bit variables in vcd_writer.sample(). 2024-10-13 01:00:40 +01:00
Akash Levy
d5ff6b4873 Update yosys-slang dep 2024-10-12 16:03:51 -07:00
Akash Levy
db95ed6c77
Merge branch 'YosysHQ:main' into main 2024-10-12 16:02:50 -07:00
Robin Ole Heinemann
0f762f75a6 cxxrtl: fix vcd writer scope handling
The vcd writer incorrectly treated two scope vectors as the same, whenever
they have the same length of entries and the last item matches.
This is however not always true, for example consider a current_scope of
["top", "something0", "same"]
and a scope of
["top", "something1", "same"]
2024-10-12 14:41:53 +01:00
Miodrag Milanović
a8f4bc2904
Merge pull request #4659 from YosysHQ/emil/cxxopts-https
cxxopts: https submodule
2024-10-12 14:07:01 +02:00
Emil J. Tywoniak
999d1f40bc cxxopts: https submodule 2024-10-12 10:32:09 +02:00
Emil J
5c9b2df689
Merge pull request #4616 from YosysHQ/emil/cxxopts
driver: replace getopt with cxxopts, replace -B, clean up help
2024-10-12 00:52:34 -07:00
Akash Levy
eae66c7d6a Update deps 2024-10-11 15:49:42 -07:00