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Author	SHA1	Message	Date
Eddie Hung	a97d30d2f8	Merge pull request #1194 from cr1901/miss-semi ... Fix missing semicolon in Windows-specific code in aigerparse.cc.	2019-07-14 13:36:34 -07:00
William D. Jones	da5d64d71e	Fix missing semicolon in Windows-specific code in aigerparse.cc. ... Signed-off-by: William D. Jones <thor0505@comcast.net>	2019-07-14 13:52:27 -04:00
Roman-Parise	f7ab7a418c	Updated FreeBSD dependencies in README.md	2019-07-14 09:25:07 -07:00
whitequark	2de7e92bb8	opt_lut: make less chatty.	2019-07-13 16:49:56 +00:00
Eddie Hung	9b91d815b5	If ConstEval fails do not log_abort() but return gracefully	2019-07-13 04:13:57 -07:00
Eddie Hung	ab3917d079	Error out if enable > dbits	2019-07-13 03:39:23 -07:00
Eddie Hung	d032198fac	ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT	2019-07-13 01:11:00 -07:00
Eddie Hung	fb062c3426	Add comment	2019-07-13 00:52:21 -07:00
Eddie Hung	41243a53b3	Update test with more accurate LUT mask	2019-07-12 21:00:59 -07:00
Eddie Hung	e9bdc86c0e	duplicate -> clone	2019-07-12 19:33:02 -07:00
Eddie Hung	be0cb7f4b8	More cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	7d583f9e57	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	83f23a24a8	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	1adbfb5533	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	39a7c7c54c	More cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	91c07be196	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	399e1ec870	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	58dbb28fd3	Cleanup	2019-07-12 19:30:18 -07:00
Eddie Hung	7dc15bdd2d	Do not double count cells in abc	2019-07-12 08:22:26 -07:00
Clifford Wolf	463f710066	Merge pull request #1183 from whitequark/ice40-always-relut ... synth_ice40: switch -relut to be always on	2019-07-12 10:48:00 +02:00
Eddie Hung	7a912f22b2	Use Const::from_string() not its constructor...	2019-07-12 01:32:10 -07:00
Eddie Hung	28274dfb09	Off by one	2019-07-12 01:17:53 -07:00
Eddie Hung	e0e5d7d68e	Fix spacing	2019-07-12 01:15:22 -07:00
Eddie Hung	4de03bd5e6	Remove double push	2019-07-12 01:08:48 -07:00
Eddie Hung	62ac5ebd02	Map to and from this box if -abc9	2019-07-12 00:53:01 -07:00
Eddie Hung	0f5bddcd79	ice40_opt to handle this box and opt back to SB_LUT4	2019-07-12 00:52:31 -07:00
Eddie Hung	a79ff2501e	Add new box to cells_sim.v	2019-07-12 00:52:19 -07:00
Eddie Hung	c6e16e1334	_ABC macro will map and unmap to this new box	2019-07-12 00:51:37 -07:00
Eddie Hung	fc3d74616f	Combine SB_CARRY+SB_LUT into one $__ICE40_CARRY_LUT4 box	2019-07-12 00:50:42 -07:00
whitequark	b700a4b1c5	synth_ice40: switch -relut to be always on.	2019-07-11 20:18:41 +00:00
whitequark	a8c5f7f41e	synth_ice40: fix help text typo. NFC.	2019-07-11 20:18:41 +00:00
Eddie Hung	19c1c3cfa3	Merge pull request #1182 from koriakin/xc6s-bram ... synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 12:55:35 -07:00
Eddie Hung	931adbaf74	Merge pull request #1185 from koriakin/xc-ff-init-vals ... xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 12:55:14 -07:00
Marcin Kościelnicki	a9efacd01d	xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Vivado.	2019-07-11 21:13:12 +02:00
Eddie Hung	c0abd18799	Enable &mfs for abc9, even if it only currently works for ice40	2019-07-11 08:49:06 -07:00
Marcin Kościelnicki	ce250b341c	synth_xilinx: Initial Spartan 6 block RAM inference support.	2019-07-11 14:45:48 +02:00
Clifford Wolf	9112850800	Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark ... write_verilog: write RTLIL::Sa aka - as Verilog ?	2019-07-11 07:25:52 +02:00
Clifford Wolf	fd3d5cefad	Merge pull request #1179 from whitequark/attrmap-proc ... attrmap: also consider process, switch and case attributes	2019-07-11 07:23:28 +02:00
Eddie Hung	bb2144ae73	Merge pull request #1180 from YosysHQ/eddie/no_abc9_retime ... Error out if -abc9 and -retime specified	2019-07-10 14:38:13 -07:00
Eddie Hung	2f990a7319	Merge pull request #1148 from YosysHQ/xc7mux ... synth_xilinx to infer wide multiplexers using new '-widemux <min>' option	2019-07-10 14:38:00 -07:00
Eddie Hung	6bbd286e03	Error out if -abc9 and -retime specified	2019-07-10 12:47:48 -07:00
Eddie Hung	58bb84e5b2	Add some spacing	2019-07-10 12:32:33 -07:00
Eddie Hung	521971e32e	Add some ASCII art explaining mux decomposition	2019-07-10 12:20:04 -07:00
whitequark	ea447220da	attrmap: also consider process, switch and case attributes.	2019-07-10 12:30:53 +00:00
Clifford Wolf	c66b4b9131	Merge pull request #1177 from YosysHQ/clifford/async ... Fix clk2fflogic adff reset semantic to negative hold time on reset	2019-07-10 08:48:20 +02:00
Eddie Hung	e573d024a2	Call muxpack and pmux2shiftx before cmp2lut	2019-07-09 21:26:38 -07:00
Eddie Hung	1122a2e067	Fix first divergence in #1178	2019-07-09 15:49:16 -07:00
Eddie Hung	c55530b901	Restore opt_clean back to original place	2019-07-09 14:29:58 -07:00
Eddie Hung	5b48b18d29	Restore missing techmap -map +/cmp2lut.v with LUT_WIDTH=6	2019-07-09 14:28:54 -07:00
David Shah	27b27b8781	synth_ecp5: Fix typo in copyright header ... Signed-off-by: David Shah <dave@ds0.me>	2019-07-09 22:26:10 +01:00