mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity
6682 commits 123 branches 59 tags 44 MiB
Commit graph

6682 commits

This branch
This branch
All branches
Author SHA1 Message Date
Eddie Hung
1467761060 Fix typo that's gone unnoticed for 5 months!?! 2019-08-29 10:33:28 -07:00
Clifford Wolf
89695fd3ab Bump YOSYS_VER 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-29 12:05:26 +02:00
Eddie Hung
fc727fa5c9
Merge pull request #1334 from YosysHQ/clifford/async2synclatch 
Add $dlatch support to async2sync
 2019-08-28 12:36:06 -07:00
Eddie Hung
9314a0a42e Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor 2019-08-28 10:51:39 -07:00
David Shah
13424352cc
Merge pull request #1332 from YosysHQ/dave/ecp5gsr 
ecp5: Add GSR and SGSR support
 2019-08-28 12:44:02 +01:00
Clifford Wolf
c84fef92df
Merge pull request #1335 from YosysHQ/clifford/paramap 
Add "paramap" pass
 2019-08-28 10:35:47 +02:00
Clifford Wolf
47ffbf554e Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c Add "paramap" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:03:27 +02:00
Clifford Wolf
c499dc3e73 Add $dlatch support to async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 09:45:22 +02:00
Clifford Wolf
70c0cddb1e
Merge pull request #1325 from YosysHQ/eddie/sat_init 
In sat: 'x' in init attr should be ignored
 2019-08-28 00:18:14 +02:00
Marcin Kościelnicki
d361f5ab79 xilinx: Add SRLC16E primitive. 
Fixes #1331.
 2019-08-27 20:27:12 +02:00
Eddie Hung
eab3c1432b
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap 
Add clock buffer insertion pass, improve iopadmap.
 2019-08-27 10:19:27 -07:00
Eddie Hung
28133432be Ignore all 1'bx in (* init *) 2019-08-27 09:24:59 -07:00
Eddie Hung
00387f3927 Revert to using clean 2019-08-27 09:24:32 -07:00
Marcin Kościelnicki
5fb4b12cb5 improve clkbuf_inhibit propagation upwards through hierarchy 2019-08-27 17:26:47 +02:00
David Shah
fc001b4731 ecp5: Add GSR support 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-27 13:07:06 +01:00
Clifford Wolf
fdbcf78909 Add "make bumpversion" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-27 10:15:25 +02:00
Eddie Hung
528f1c8687 Improve tests to check that clkbuf is connected to expected 2019-08-26 13:45:16 -07:00
Eddie Hung
a098205479 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-26 13:25:17 -07:00
Eddie Hung
bd3773a17f Remove dupe in CHANGELOG, missing end quote 2019-08-26 10:44:23 -07:00
Clifford Wolf
8a4c6e6563 Merge tag 'yosys-0.9' 2019-08-26 11:14:22 +02:00
Clifford Wolf
1979e0b1f2 Yosys 0.9 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-26 10:37:53 +02:00
Clifford Wolf
a3de83ef4a
Merge pull request #1112 from acw1251/pyosys_sigsig_issue 
Fixed pyosys commands returning RTLIL::SigSig
 2019-08-25 11:22:02 +02:00
Eddie Hung
dc87372a97 Wire with init on FF part, 1'bx on non-FF part 2019-08-24 15:05:44 -07:00
Clifford Wolf
dc9c47b5af
Merge pull request #1327 from YosysHQ/clifford/pmgen 
Add pmgen slices and choices
 2019-08-24 08:38:49 +02:00
Eddie Hung
d7051b90de Add undocumented feature 2019-08-23 16:41:32 -07:00
Eddie Hung
967a36c125 indo -> into 2019-08-23 13:16:50 -07:00
Eddie Hung
4a4e28b55e Revert earliest to gcc-4.8, compile iverilog with default compiler 2019-08-23 12:29:57 -07:00
Eddie Hung
b3dc28cf65 Revert "Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?!" 
This reverts commit c82b2fa31f.
 2019-08-23 12:29:57 -07:00
Eddie Hung
fcb102d60e Remove .0 from clang-8.0 2019-08-23 12:29:57 -07:00
Eddie Hung
fdc438e551 Bump to gcc-5 as `__warn_memset_zero_len' symbol not in 16.04!?! 2019-08-23 12:29:57 -07:00
Eddie Hung
bf40f2f895 bionic -> xenial as its on whitelist 2019-08-23 12:29:57 -07:00
Eddie Hung
43927e5910 Bump gcc from 4.8 to 4.9 as undefined reference 
... to `__warn_memset_zero_len'.
Also remove gcc-6, bump gcc-7 to gcc-9, clang from 5.0 to 8.0
 2019-08-23 12:29:50 -07:00
Eddie Hung
20f4d191b5 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:24:19 -07:00
Eddie Hung
509c353fe9 Forgot one 2019-08-23 11:23:50 -07:00
Eddie Hung
0d0ad15898 Merge branch 'master' into mwk/xilinx_bufgmap 2019-08-23 11:23:31 -07:00
Eddie Hung
a270af00cc Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
Eddie Hung
a0d85393e3 Check clkbuf_inhibit=1 is ignored for custom selection 2019-08-23 11:15:26 -07:00
Eddie Hung
619f2414e5 clkbufmap to only check clkbuf_inhibit if no selection given 2019-08-23 11:14:42 -07:00
Eddie Hung
5628e2ec53 Add simple clkbufmap tests 2019-08-23 11:10:02 -07:00
Eddie Hung
d62c10d641 tests/techmap/run-test.sh to cope with *.ys 2019-08-23 11:09:50 -07:00
Eddie Hung
4c0404ae02 Mention clkbuf_inhibit can be overridden 2019-08-23 10:24:59 -07:00
Eddie Hung
4d89c3f468 Review comment from @cliffordwolf 2019-08-23 10:03:41 -07:00
Eddie Hung
6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Miodrag Milanovic
55aa444e05 Make macOS depenency clear 2019-08-23 09:15:50 -07:00
Eddie Hung
bb2d5bc4f8
Merge pull request #1326 from mmicko/doc-update 
Make macOS dependency clear
 2019-08-23 09:12:58 -07:00
Eddie Hung
10c41a5cf5 Blocking assignment 2019-08-23 09:11:04 -07:00
Clifford Wolf
55bf8f69e0 Fix port hanlding in pmgen 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-23 16:26:54 +02:00
Clifford Wolf
adb81ba386 Add pmgen slices and choices 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-23 16:15:50 +02:00
Miodrag Milanovic
c618ae43b9 Make macOS depenency clear 2019-08-23 10:37:50 +02:00