Roland Coeurjoly
5ea2c6e6e5
Assume x values for missing signal data in FST
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Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-10-02 12:08:48 +02:00
Martin Povišer
ec42b42bd9
cellmatch: Size the lut attribute
2024-10-02 11:29:54 +02:00
Emil J. Tywoniak
997cb30f1f
cxxrtl: test stream operator
2024-10-01 13:25:07 +02:00
Roland Coeurjoly
76c615b2ae
Fix: handle VCD variable references with and without whitespace
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Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-10-01 11:51:20 +02:00
github-actions[bot]
1bf908dea8
Bump version
2024-10-01 00:23:05 +00:00
Miodrag Milanović
500db6acc6
Merge pull request #4621 from RCoeurjoly/roland/get_vcd2fst
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Add "Get vcd2fst" step to test-yosys job
2024-09-30 21:38:39 +02:00
Mohamed Gaber
35c8ad61ac
cli/python: error-checking, python interpreter bugfix
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* Less brittle method of adding script dirname to sys.path
* Check if scriptfp successfully opens before using it
* Move `log_error` to after `PyErr_Print()` is called
2024-09-30 17:38:43 +03:00
Roland Coeurjoly
5fca9b867d
Add Get vcd2fst step to test-yosys job
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Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
2024-09-30 16:25:32 +02:00
github-actions[bot]
59404f8ce5
Bump version
2024-09-30 00:21:26 +00:00
rherveille
ce7db661a8
Added cast to type support ( #4284 )
2024-09-29 17:03:01 -04:00
George Rennie
0572f8806f
opt_reduce: add test for constant $reduce_and/or not being zero width
2024-09-25 16:28:41 +01:00
George Rennie
023f029dcf
opt_reduce: keep at least one input to $reduce_or/and cells
2024-09-25 16:21:19 +01:00
George Rennie
e105cae4a9
opt_demorgan: add test for zero width cell
2024-09-25 16:10:16 +01:00
Martin Povišer
3e3515e7d9
log: Never silence log_cmd_error
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Add extra handling to arrange for `log_cmd_error` never being silenced
by the command line `-v N` option. Similar path for `log_error` exists
already.
2024-09-24 17:47:46 +02:00
George Rennie
58af70624f
opt_demorgan: skip zero width cells
2024-09-24 14:24:59 +01:00
George Rennie
b788de9329
smtbmc: escape path identifiers
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* also changes the print format for cover statements to be more uniform
with the asserts, allowing easier parsing of cover path
* this allows diambiguation of properties with the same name but
different paths (see https://github.com/YosysHQ/sby/issues/296 )
2024-09-24 03:01:49 +01:00
N. Engelhardt
8e1e2b9a39
Merge pull request #4495 from povik/check-avert-costly-detail
2024-09-23 15:19:48 +02:00
Martin Povišer
9018d06a33
quicklogic: Avoid carry chains in division mapping
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The default mapping rules for division-like operations (div/divfloor/
mod/modfloor) invoke subtractions which can get mapped to carry chains
in FPGA flows. Optimizations across carry chains are weak, so in
practice this ends up too costly compared to implementing the division
purely in soft logic.
For this reason arrange for `techmap.v` ignoring division operations
under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry
chains for divisions.
2024-09-19 12:18:47 +02:00
Martin Povišer
f168b2f4b1
read_xaiger2: Update box handling
2024-09-18 16:55:02 +02:00
Martin Povišer
3a1b003cc3
celltypes: Fix $buf eval
2024-09-18 16:55:02 +02:00
Martin Povišer
5f8d7ff170
Start new write_xaiger2 backend for export w/ boxes
2024-09-18 16:55:02 +02:00
Martin Povišer
ea765686b6
aiger2: Adjust hierarchy/port handling
2024-09-18 16:55:02 +02:00
Martin Povišer
2a3e907da8
aiger2: Adjust typing
2024-09-18 16:42:56 +02:00
Martin Povišer
72d65063c3
aiger2: Ignore benign cells
2024-09-18 16:42:56 +02:00
Martin Povišer
1ab7f29933
Start read_xaiger2 -sc_mapping
2024-09-18 16:42:56 +02:00
Martin Povišer
6cecf19ff4
aiger2: Ingest $bmux
2024-09-18 16:42:56 +02:00
Martin Povišer
1cfb9023c4
aiger2: Use REDUCE for reduction ops
2024-09-18 16:42:56 +02:00
Martin Povišer
6c1fa45995
aiger2: Ingest $pmux
2024-09-18 16:42:56 +02:00
Martin Povišer
d5756eb9be
tests: Add trivial liberty -unit_delay test
2024-09-18 16:17:03 +02:00
Martin Povišer
31476e89b6
tests: Avoid temporary script file
2024-09-18 16:17:03 +02:00
Martin Povišer
4976abb867
read_liberty: Optionally import unit delay arcs
2024-09-18 16:17:03 +02:00
github-actions[bot]
4d581a97d6
Bump version
2024-09-18 00:19:41 +00:00
Martin Povišer
9db1ca83fc
aiger2: Drop empty_lit() as a function
2024-09-17 13:58:07 +02:00
Martin Povišer
dbc937b2a7
aiger2: Describe supported cells in help
2024-09-17 13:55:58 +02:00
Martin Povišer
e4b24e8200
aiger2: Fix literal typing
2024-09-17 13:55:58 +02:00
Martin Povišer
8e29675a23
aiger2: Support $bwmux, comparison operators
2024-09-17 13:55:58 +02:00
Martin Povišer
d7128cb787
aiger2: Use shorthands
2024-09-17 13:55:58 +02:00
Martin Povišer
e59387e5a9
aiger2: Add aigsize as a second user of index
2024-09-17 13:55:58 +02:00
Martin Povišer
de8a2fb936
aiger2: Fix duplicate symbols on multibit ports
2024-09-17 13:55:58 +02:00
Martin Povišer
5671c10173
aiger2: Add strashing option
2024-09-17 13:55:58 +02:00
Martin Povišer
fa39227416
aiger2: Support $pos
2024-09-17 13:55:58 +02:00
Martin Povišer
fb26945a20
Start an 'aiger2' backend
2024-09-17 13:55:58 +02:00
Martin Povišer
4cfdb7ab50
Adjust operation naming in aigmap test
2024-09-17 13:55:58 +02:00
Martin Povišer
a553b7c0c7
Merge pull request #3967 from YosysHQ/claire/bufnorm
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Add "buffered-normalized mode", add $buf cell type, and add "bufnorm" command
2024-09-17 11:27:23 +02:00
Martin Povišer
eeffca9470
simlib: Add $buf disclaimer
2024-09-17 10:46:20 +02:00
Martin Povišer
e13ace675e
dump: Update help after option removal
2024-09-17 10:46:20 +02:00
Martin Povišer
38de01807e
Mark bufnorm experimental
2024-09-17 10:46:20 +02:00
Martin Povišer
865df26fac
Adjust buf-normalized mode
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
80119386c0
Add RTLIL "buffered-normalized mode" and improve "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
Claire Xenia Wolf
8bb70bac8d
Improvements in "bufnorm" pass
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Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-09-17 10:46:20 +02:00
