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116 commits

Author SHA1 Message Date
Emil J. Tywoniak
adb1986dc1 gzip: refactor file open failure errors 2025-04-29 10:37:35 +02:00
Krystine Sherwin
cd3b914132
Reinstate #4768
Revert the reversion so that we can fix the bugs that the PR missed.
2025-04-08 11:58:05 +12:00
Miodrag Milanović
d49364d96f
Revert "Refactor full_selection" 2025-04-07 12:11:55 +02:00
KrystalDelusion
98d4355b82
Merge pull request #4768 from YosysHQ/krys/refactor_selections
Refactor full_selection
2025-04-05 14:15:27 +13:00
Emil J. Tywoniak
7aefd4b226 gzip: back to pointers 2025-03-19 13:43:44 +01:00
Emil J. Tywoniak
d00259081d gzip: simplify uncompressed interface 2025-03-19 13:43:44 +01:00
Emil J. Tywoniak
813f909460 gzip: istream 2025-03-19 13:43:44 +01:00
Emil J. Tywoniak
4f3fdc8457 io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
Krystine Sherwin
dac2bb7d4d
Use selection helpers
Catch more uses of selection constructor without assigning a design.
2025-03-14 14:08:13 +13:00
Miodrag Milanovic
d50849ea83 Copyright year update 2025-01-21 08:48:29 +01:00
Krystine Sherwin
4ea6119734
cmdref: Move html only section inside cmd:def
Fixes missing links in body and `??` in tag/command index.
Update synth.rst to match.
2024-10-17 06:06:57 +13:00
Krystine Sherwin
b1025dbaa6
cellhelp.py: Cells can have tags
Tags are added to the list of properties when exporting to `cells.json`.
2024-10-15 07:35:41 +13:00
Krystine Sherwin
04b0ae540d
cellref: Move default help message to register.cc
Drop the default help message from rst while still displaying it on the command line.
Fix command line formatting for older style help messages.
2024-10-15 07:31:47 +13:00
Krystine Sherwin
b127ac07f8
Docs: Preliminary autocellgroup usage
Remove `/source/cell` from .gitignore.
Add a few initial cell pages.
Add YosysCellGroup documenter and cell:group directive.
Update Documenters to use nested json.
Better nested tocs for group.module.source layout.
2024-10-15 07:26:04 +13:00
Krystine Sherwin
7c5b10fe50
cellref: Add json dump
New `help -dump-cells-json <file>` to dump cells list.
Add 'group' field to SimHelper class/struct with defaults to gate_other and word_other depending on source (simcells or simlib).
Add 'unary' group to unary operator cells for testing (based on internal cell library docs page).
2024-10-15 07:25:27 +13:00
Krystine Sherwin
063a6bc2d7
register.cc: Include properties in docs 2024-10-15 07:23:45 +13:00
Krystine Sherwin
21747c468c
Docs: Improve cell_help usage
- Drop `cell_code` and instead map code lookups to the `cell_help` dict.
- Add helper functions to struct for checking and getting the right cell.
- Add `CellType` for cell to `write_cell_rst` function declaration in
  preparation for use in future.
- Iterate over `yosys_celltypes.cell_types` when exporting cell rst files,
  reporting errors for any cells defined in `cell_types` but not
  `cell_help_messages`.
2024-10-15 07:23:45 +13:00
Krystine Sherwin
f9b4e04fef
Docs: Add cell reference
Subclass the command reference code in order to support smart references to the internal cells.
2024-10-15 07:17:36 +13:00
Krystine Sherwin
c98d134662
cellhelp: Extra newline
Fix `$macc` page.
2024-10-15 07:17:35 +13:00
Krystine Sherwin
d629aa6bf1
cellhelp: Split gate-level and word-level cells 2024-10-15 07:17:35 +13:00
Krystine Sherwin
57cd8d29db
cellhelp: Add default format parse for simcells
Since `simcells.v` uses consistent formatting we can handle it specifically to help tidy up sphinx warnings about the truth tables, and instead chuck them in a code block which when printing to rst.
Also has the side effect that rst code blocks can be added manually with `//- ::` followed by a blank line.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
a2b2904ed8
cellhelp: Add source line to help
Include Source file and line number in SimHelper struct, and use it for verilog code caption in rst dump.
Also reformat python string conversion to iterate over a list of fields instead of repeating code for each.
2024-10-15 07:16:40 +13:00
Krystine Sherwin
784292626e
cellhelp: Rename short_desc to title 2024-10-15 07:16:39 +13:00
Krystine Sherwin
1e5a50ff3a
Docs: Convert write_cell_rst to use SimHelper 2024-10-15 07:16:39 +13:00
Krystine Sherwin
6bbe763845
Docs: Put cell library help strings into a struct
Allows for more expressive code when constructing help messages for cells.
Will also move extra logic in parsing help strings into the initial python parse instead of doing it in the C++ at export time.
2024-10-15 07:16:39 +13:00
Krystine Sherwin
a6641da73c
Docs: Initial version of cell_ref autogen 2024-10-15 07:16:39 +13:00
Krystine Sherwin
d2bf5a83af
Merge branch 'origin/master' into krys/docs 2024-03-18 10:39:30 +13:00
Miodrag Milanovic
5e05300e7b fix compile warning 2024-03-11 10:55:09 +01:00
Krystine Sherwin
1455941ab9
Merge branch 'master' into krys/docs 2024-03-05 05:48:46 +13:00
Martin Povišer
f7737a12ca Cut down startup banner 2024-02-22 22:14:32 +01:00
Claire Xenia Wolf
4fa314c0bd Add API to overwrite existing pass from plugin
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-01-30 17:51:11 +01:00
Krystine Sherwin
8203a01ba9
Adding custom domain for cmdref 2023-08-08 11:51:57 +12:00
Miodrag Milanovic
6574553189 Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
Miodrag Milanovic
40282576b0 Display error instead of assertion when pass exists 2023-01-09 17:02:56 +01:00
KrystalDelusion
11fe4d0862 Remove help outputs for tex
Also for old website.
2022-12-08 05:57:41 +13:00
KrystalDelusion
a14dec79eb
Rst docs conversion (#3496)
Rst docs conversion
2022-11-15 12:55:22 +01:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
whitequark
7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
whitequark
b43c282e4e Add WASI platform support.
This includes the following significant changes:
  * Patching ezsat and minisat to disable resource limiting code
    on WASM/WASI, since the POSIX functions they use are unavailable.
  * Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
    does not support spawning subprocesses (i.e. Emscripten or WASI).
    This definition hides the definition of `run_command()`.
  * Adding a new Makefile flag, DISABLE_SPAWN, present in the same
    condition. This flag disables all passes that require spawning
    subprocesses for their function.
2020-04-30 18:56:25 +00:00
Alberto Gonzalez
76c9e1c265
Use script-style heredoc syntax for REPL heredocs. 2020-04-15 16:15:51 +00:00
Alberto Gonzalez
b5ecbbef94
Allow reading file input from stdin, improving REPL experience. 2020-04-15 16:15:50 +00:00
David Shah
b8abf14376 Add ScriptPass::run_nocheck and use for abc9
Signed-off-by: David Shah <dave@ds0.me>
2020-03-09 14:34:22 +00:00
Claire Wolf
cef607c8b7 Add log_experimental() and experimental() API and "yosys -x"
Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 18:27:47 +01:00
Clifford Wolf
cd92a974f4 Add Pass::on_register() and Pass::on_shutdown()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-09 21:36:34 +01:00
Miodrag Milanovic
3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00
Miodrag Milanovic
d0493925ec Support binary files for backends, fixes #1407 2019-09-28 09:36:18 +02:00
Miodrag Milanovic
435300f930 Make read/write gzip files on macos works, fixes #1357 2019-09-26 19:35:12 +02:00
Eddie Hung
6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Clifford Wolf
c5d56fbe2d
Merge pull request #1253 from YosysHQ/clifford/check
Be less aggressive with running design->check()
2019-08-07 12:14:41 +02:00
Clifford Wolf
95a6582f34 Be less aggressive with running design->check()
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 19:21:37 +02:00