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Author	SHA1	Message	Date
AdvaySingh1	144db54c4e	Changed to inverse hashing for more flexibility	2026-02-17 11:53:06 -08:00
AdvaySingh1	f0de3ae8de	Initial sat_clockgate pass pre speed optimization	2026-02-17 11:19:18 -08:00
AdvaySingh1	cc6605f8e2	Added passing on the args into the clockgate pass so there's an icg cell for the mapping	2026-02-17 10:49:18 -08:00
AdvaySingh1	2ab34262ec	Added profiling info before and after sat_clockgate pass	2026-02-17 09:23:32 -08:00
AdvaySingh1	3567960671	Changed hashing from string to pair with vector and bool	2026-02-13 17:01:58 -08:00
AdvaySingh1	91d8241a9a	Revert "Added hashing for already seen paths. ODO: add profiling to see if this is effective" ... This reverts commit 56502440b3.	2026-02-13 16:34:38 -08:00
AdvaySingh1	5ce8aada27	Added profiling for literal count	2026-02-13 16:34:15 -08:00
AdvaySingh1	3442bc3a85	Changed indexing to be based on the literal ID in EZSat and sorted to allow better hashing	2026-02-13 16:15:31 -08:00
AdvaySingh1	80fbdf7e6a	Removed duplication of vectors and called clockgate pass post creating enable signals	2026-02-13 15:33:45 -08:00
AdvaySingh1	56502440b3	Added hashing for already seen paths. ODO: add profiling to see if this is effective	2026-02-13 15:32:54 -08:00
Akash Levy	5debd619e5	Add workaround for Liberty duplication	2026-02-13 06:51:42 -08:00
Miodrag Milanović	ac96f318ef	Merge pull request #5676 from YosysHQ/emil/unit-test-by-default ... Run unit tests on make test	2026-02-13 15:02:50 +01:00
Akash Levy	0485576632	Revert rtlil changes	2026-02-13 04:14:14 -08:00
Akash Levy	2b247d165b	Merge from main	2026-02-13 04:14:08 -08:00
Akash Levy	b8d83c1d5b	Fix cell naming issues	2026-02-13 01:05:51 -08:00
Akash Levy	e81b5b810d	Lack of node retention should only be a warning	2026-02-13 01:04:59 -08:00
AdvaySingh1	fca02c94df	Notes for TODOS	2026-02-12 17:04:50 -08:00
github-actions[bot]	e2f0c4d9a0	Bump version	2026-02-13 00:35:27 +00:00
AdvaySingh1	feffbbe32c	Added initial impl based on OpenROAD	2026-02-12 16:12:50 -08:00
AdvaySingh1	d7277fcb3a	Added explanation for safe-gating vs exact-gating	2026-02-12 15:20:39 -08:00
AdvaySingh1	0396bf48d1	Added notes.txt	2026-02-12 14:28:37 -08:00
AdvaySingh1	e4734e6ca9	Added comments explaining the MUX network repair Idea to see if there's a combinational circuit out of the input values which can serve as the enable signal	2026-02-12 12:49:15 -08:00
AdvaySingh1	514c01efd2	Added prune expressions list TODO	2026-02-12 12:14:25 -08:00
AdvaySingh1	745f17a34e	Changed input_set_is_enable_exact to XOR Mitter	2026-02-12 11:10:10 -08:00
Miodrag Milanovic	bb7aa7d208	Cleanup of yml files	2026-02-12 14:56:45 +01:00
Miodrag Milanović	e4b32d6aae	Merge pull request #5670 from max-kudinov/gowin_mult ... Gowin: Add DSP inference for GW1N and GW2A	2026-02-12 14:30:27 +01:00
Miodrag Milanovic	e5b3e9fc1f	This one should run only vanilla-tests	2026-02-12 14:08:49 +01:00
Miodrag Milanovic	c6e48f4bea	These are tests from other Makefile	2026-02-12 14:06:08 +01:00
Miodrag Milanovic	cc79c6a761	Support building out of tree, but keep always in tests/unit	2026-02-12 12:17:07 +01:00
Maxim Kudinov	b055ea05fd	gowin: dsp: Add mult inference tests	2026-02-12 14:12:32 +03:00
Maxim Kudinov	5b94a97fb3	gowin: synth_gowin: Add -nodsp option	2026-02-12 13:58:47 +03:00
Maxim Kudinov	542b29fa6a	gowin: synth_gowin: Merge flatten label with coarse	2026-02-12 13:58:47 +03:00
Maxim Kudinov	5ea073d45e	gowin: format MULT instances	2026-02-12 13:35:49 +03:00
Miodrag Milanović	9b9e7b5ae3	Merge pull request #3389 from uwsampl/support-parameter-default-values-in-json-frontend-and-verilog-backend ... Support parameter default values in JSON frontend and Verilog backend	2026-02-12 10:17:56 +01:00
Miodrag Milanović	ce5321da8c	Merge pull request #5682 from YosysHQ/update_abc ... Update ABC as per 2026-02-11	2026-02-12 08:05:23 +01:00
AdvaySingh1	481e49954d	Added notes for a fixed input_set_is_enable implementation	2026-02-11 17:05:13 -08:00
github-actions[bot]	1319112913	Bump version	2026-02-12 00:32:36 +00:00
AdvaySingh1	532d1d45a8	Resolved adding SigBits from Q using static EXCLUDE_Q_FROM_ENABLE knob	2026-02-11 15:08:49 -08:00
AdvaySingh1	4ca4392e9b	Simplied recursion in sat_clockgate pass	2026-02-11 14:56:46 -08:00
AdvaySingh1	19060eeee7	Added TODO for how to add the COI set	2026-02-11 14:40:32 -08:00
AdvaySingh1	143a860673	Added future TODOs	2026-02-11 14:39:47 -08:00
AdvaySingh1	da8febc3b7	Added to notes.txt	2026-02-11 14:22:26 -08:00
AdvaySingh1	d2300b2a9f	Added nodes for the MITER	2026-02-11 14:19:29 -08:00
AdvaySingh1	dd3f2e370c	Fixed naming for bfs_find_potential_enable_inputs	2026-02-11 12:31:13 -08:00
AdvaySingh1	5b384511f2	Added initial SatClockgateWorker	2026-02-11 11:02:15 -08:00
AdvaySingh1	9e544aa95c	Added pseudocode for create_ce_logic	2026-02-11 11:01:49 -08:00
AdvaySingh1	b4cd82bacf	Added initial printing of the clocks with dump_flipflops_to_file	2026-02-11 10:56:07 -08:00
AdvaySingh1	5aeb19fb66	Added initial version 1 pseudocode	2026-02-11 10:55:43 -08:00
AdvaySingh1	e4f69cba30	Initialized notes	2026-02-11 09:53:03 -08:00
Gus Smith	7a0774c3bb	Don't dump params by default	2026-02-11 08:33:39 -08:00