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46 commits

Author SHA1 Message Date
Robert O'Callahan
2654bd5355 Compute is_port in AbcPass without iterating through all cells and wires in the module every time we run ABC. 
This does not scale when we run ABC thousands of times in a single AbcPass.
 2025-08-14 22:29:45 +00:00
Emil J. Tywoniak
a58481e9b7 mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
Emil J. Tywoniak
b9b9515bb0 hashlib: hash_eat -> hash_into 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak
d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Emil J. Tywoniak
583db7b15e sigmap: comments 2024-07-18 16:02:11 +02:00
Claire Xenia Wolf
72787f52fc Fixing old e-mail addresses and deadnames 
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
 2021-06-08 00:39:36 +02:00
Eddie Hung
6ca7844cec kernel: const Wire* overload -> Wire* !!! 2020-03-26 16:21:30 -07:00
Eddie Hung
8c45ea9f0e kernel: use const reference for SigSet too 2020-03-17 10:22:33 -07:00
Eddie Hung
a076052fe4 kernel: SigPool to use const& + overloads to prevent implicit SigSpec 2020-03-12 16:00:34 -07:00
Eddie Hung
9a84e4711c Spacing 2019-09-13 16:30:44 -07:00
Eddie Hung
5473e597bf Use template specialisation 2019-09-13 11:13:57 -07:00
Eddie Hung
c487a8ff25 Grammar 2019-09-12 12:00:34 -07:00
Eddie Hung
c05a403dd1 static_assert to enforce this going forward 2019-09-12 11:45:17 -07:00
Clifford Wolf
01bcc5663f SigMap performance improvement 2016-02-01 10:10:20 +01:00
Clifford Wolf
276101f032 Re-added SigMap::allbits() 2015-11-30 19:43:52 +01:00
Clifford Wolf
1e32e4bdae Improved SigMap performance 2015-10-28 11:21:55 +01:00
Clifford Wolf
e69efec588 Improvements in new SigMap 2015-10-28 00:39:53 +01:00
Clifford Wolf
f3db70d2f3 Removed old SigMap implementation 2015-10-27 15:09:44 +01:00
Clifford Wolf
09b4050f2e Added hashlib::mfp and new SigMap 2015-10-27 15:04:47 +01:00
Clifford Wolf
ee8f6f31f4 Added SigMap::allbits() 2015-08-31 16:42:19 +02:00
Clifford Wolf
6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf
bc86b4a7e9 Added "equiv_induct -undef" 2015-01-31 13:58:04 +01:00
Clifford Wolf
7d843adef9 dict/pool changes in opt_clean 2014-12-29 04:06:52 +01:00
Clifford Wolf
6ce6689b63 Using Yosys::dict and Yosys::pool in sigtools.h 2014-12-26 22:08:44 +01:00
Clifford Wolf
4569a747f8 Renamed SIZE() to GetSize() because of name collision on Win32 2014-10-10 17:07:24 +02:00
Clifford Wolf
d13eb7e099 Added ModIndex helper class, some changes to RTLIL::Monitor 2014-08-01 17:14:32 +02:00
Clifford Wolf
1cb25c05b3 Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
Clifford Wolf
7bd2d1064f Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
Clifford Wolf
0c86d6106c Added SigPool::check(bit) 2014-07-27 15:38:02 +02:00
Clifford Wolf
b7dda72302 Changed users of cell->connections_ to the new API (sed command) 
git grep -l 'connections_' | xargs sed -i -r -e '
	s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
	s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
	s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
	s/(->|\.)connections_.push_back/\1connect/g;
	s/(->|\.)connections_/\1connections()/g;'
 2014-07-26 15:58:23 +02:00
Clifford Wolf
cc4f10883b Renamed RTLIL::{Module,Cell}::connections to connections_ 2014-07-26 11:58:03 +02:00
Clifford Wolf
a62c21c9c6 Removed RTLIL::SigSpec::expand() method 2014-07-23 19:34:51 +02:00
Clifford Wolf
ec923652e2 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3 2014-07-23 09:52:55 +02:00
Clifford Wolf
a8d3a68971 Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3 2014-07-23 09:49:43 +02:00
Clifford Wolf
115dd959d9 SigSpec refactoring: More cleanups of old SigSpec use pattern 2014-07-22 23:50:21 +02:00
Clifford Wolf
28b3fd05fa SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw() 2014-07-22 20:58:44 +02:00
Clifford Wolf
4b4048bc5f SigSpec refactoring: using the accessor functions everywhere 2014-07-22 20:39:37 +02:00
Clifford Wolf
a233762a81 SigSpec refactoring: renamed chunks and width to __chunks and __width 2014-07-22 20:39:37 +02:00
Clifford Wolf
1c288adcc0 Some "const" cleanups in SigMap 2014-07-19 15:32:39 +02:00
Clifford Wolf
05483619f0 Some fixes to improve determinism 2013-08-09 12:42:32 +02:00
Clifford Wolf
117489f95a Fixed SigPool::del() method 2013-08-06 15:04:24 +02:00
Clifford Wolf
c681c17038 Improved auto-detection of -show signals in sat_solve 2013-06-08 09:34:36 +02:00
Clifford Wolf
89f009d171 Added additional functionality and cleanups in sigtools.h and celltypes.h 2013-03-15 10:22:23 +01:00
Clifford Wolf
f28b6aff40 Implemented basic functionality of "extract" pass 2013-02-27 16:27:20 +01:00
Clifford Wolf
7764d0ba1d initial import 2013-01-05 11:13:26 +01:00