Eddie Hung
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086b6560b4
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Typo
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2019-05-26 03:17:20 -07:00 |
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Eddie Hung
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66701c5fcc
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Muck about with LUT delays some more
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2019-05-26 02:52:48 -07:00 |
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Eddie Hung
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823153e418
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Combine ABC_COMMAND_LUT
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2019-05-26 02:47:06 -07:00 |
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Eddie Hung
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32a4c10c0d
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Fix "a" extension
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2019-05-26 02:44:36 -07:00 |
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Eddie Hung
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01684643b6
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Fix "write_xaiger", and to write each box contents into holes
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2019-05-25 22:34:50 -07:00 |
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Eddie Hung
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73c98f2ae2
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-25 20:50:47 -07:00 |
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Clifford Wolf
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a90eec12c9
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Merge pull request #1041 from YosysHQ/clifford/fix1040
Fix handling of offset and upto module ports in write_blif
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2019-05-25 19:17:05 +02:00 |
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Clifford Wolf
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6352df42ae
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Fix handling of offset and upto module ports in write_blif, fixes #1040
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-25 17:45:14 +02:00 |
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Eddie Hung
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ca5774ed40
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Try new LUT delays
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2019-05-24 20:39:55 -07:00 |
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Eddie Hung
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6ad09bfcea
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Add &fraig and &mfs back
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2019-05-24 15:10:18 -07:00 |
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Eddie Hung
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60af2ca94d
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Transpose CARRY4 delays
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2019-05-24 14:09:15 -07:00 |
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Clifford Wolf
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b7dd7c2dcd
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Add proper error message for btor recursion_guard
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-24 16:22:34 +02:00 |
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Eddie Hung
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52e9036d39
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-23 13:38:04 -07:00 |
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Eddie Hung
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68359bcd6f
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Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux
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2019-05-23 13:37:53 -07:00 |
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Eddie Hung
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67a4850e35
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Merge pull request #1036 from YosysHQ/eddie/xilinx_dram
Add "min bits" and "min wports" to xilinx dram rules
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2019-05-23 13:13:10 -07:00 |
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Eddie Hung
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5ac7e38d0a
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Fix spacing
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2019-05-23 12:58:30 -07:00 |
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Eddie Hung
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99a3fee8f4
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Add "min bits" and "min wports" to xilinx dram rules
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2019-05-23 11:32:28 -07:00 |
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Eddie Hung
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47f9ea142f
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Add opt_rmdff tests
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2019-05-23 11:26:38 -07:00 |
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Eddie Hung
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50ed34a6d0
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opt_rmdff to work on $dffe and $_DFFE_*
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2019-05-23 11:26:18 -07:00 |
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Eddie Hung
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ae89e6ab26
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Add whitebox support to DRAM
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2019-05-23 08:58:57 -07:00 |
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Clifford Wolf
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ca46947354
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Merge pull request #1031 from mdaiter/optimizeLookupTableBtor
Optimize numberOfPermutations
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2019-05-23 13:52:48 +02:00 |
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Matthew Daiter
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f0ff31ceea
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Optimize numberOfPermutations
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2019-05-22 17:29:50 -04:00 |
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Clifford Wolf
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5c164d0863
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Merge pull request #1019 from YosysHQ/clifford/fix1016
Add "wreduce -keepdc"
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2019-05-22 13:29:04 +02:00 |
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Clifford Wolf
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84d91420e4
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Merge pull request #1021 from ucb-bar/fixfirrtl_shr,neg
Fix static shift operands, neg result type, minor formatting
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2019-05-22 12:01:19 +02:00 |
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Eddie Hung
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4f44e3399b
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shift register inference before mux
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2019-05-22 02:36:28 -07:00 |
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Eddie Hung
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9b1078b9bd
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Fix/workaround symptom unveiled by #1023
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2019-05-21 18:50:02 -07:00 |
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Eddie Hung
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cb24d23b6d
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Merge pull request #1024 from YosysHQ/eddie/fix_Wmissing_braces
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2019-05-21 18:20:58 -07:00 |
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Eddie Hung
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7057753427
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Rename label
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2019-05-21 18:20:31 -07:00 |
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Eddie Hung
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b5a29460b9
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Try again
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2019-05-21 17:20:19 -07:00 |
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Eddie Hung
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1bff09f2ff
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Fix warning
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2019-05-21 16:26:20 -07:00 |
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Eddie Hung
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ee8435b820
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Instead of MUXCY/XORCY use CARRY4 (with timing)
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2019-05-21 16:19:45 -07:00 |
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Eddie Hung
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0f094fba08
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Pad all boxes so that all input/output connections specified
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2019-05-21 16:19:23 -07:00 |
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Eddie Hung
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36a219063a
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Modify LUT area cost to be same as old abc
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2019-05-21 14:31:19 -07:00 |
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Eddie Hung
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fb09c6219b
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-21 14:21:00 -07:00 |
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Jim Lawson
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a5131e2896
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Fix static shift operands, neg result type, minor formatting
Static shift operands must be constants.
The result of FIRRTL's neg operator is signed.
Fix poor indentation for gen_read().
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2019-05-21 13:04:56 -07:00 |
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Jim Lawson
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489c555b41
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Merge remote-tracking branch 'upstream/master'
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2019-05-21 12:47:55 -07:00 |
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Clifford Wolf
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c4b8575f43
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Add "wreduce -keepdc", fixes #1016
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-20 15:36:13 +02:00 |
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Clifford Wolf
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c907899422
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Merge pull request #1017 from Kmanfi/bigger_verilog_files
Read bigger Verilog files.
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2019-05-18 16:54:47 +02:00 |
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Kaj Tuomi
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48ddbe52fb
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Read bigger Verilog files.
Hit parser limit with 3M gate design. This commit fix it.
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2019-05-18 14:20:30 +03:00 |
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Clifford Wolf
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b6345b111d
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Merge pull request #1013 from antmicro/parameter_attributes
Support for attributes on parameters and localparams for Verilog frontend
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2019-05-16 14:21:18 +02:00 |
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Maciej Kurc
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1f52332b8d
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Added tests for Verilog frontent for attributes on parameters and localparams
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-05-16 12:53:43 +02:00 |
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Maciej Kurc
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ce4a0954bc
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Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-05-16 12:44:16 +02:00 |
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Clifford Wolf
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c9def5407c
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Merge pull request #1012 from YosysHQ/clifford/sigspecrw
Another rounds of opt_clean improvements
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2019-05-15 21:00:56 +02:00 |
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Clifford Wolf
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a21a84b3b4
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Improvements in opt_clean
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-15 16:01:28 +02:00 |
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Clifford Wolf
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287de4b848
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Add rewrite_sigspecs2, Improve remove() wires
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-15 16:01:00 +02:00 |
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Clifford Wolf
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f67ec1b235
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Do not leak file descriptors in cover.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-05-15 13:51:02 +02:00 |
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Clifford Wolf
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4fd0e11214
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Merge pull request #1011 from hzeller/fix-constructing-string-from-int
Fix two instances of integer-assignment to string.
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2019-05-15 13:35:52 +02:00 |
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Clifford Wolf
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64b604207d
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Merge pull request #1010 from hzeller/yacc-self-contained
Make the generated *.tab.hh include all the headers needed
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2019-05-15 13:29:55 +02:00 |
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Clifford Wolf
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36841f3911
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Merge pull request #1008 from thasti/fix_libyosys_build
Create $(LIBDIR) to fix broken build in isolated environments
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2019-05-15 13:28:52 +02:00 |
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David Shah
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3ef88ffbb2
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Merge pull request #1005 from smunaut/ice40_hfosc_trim
ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC
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2019-05-15 08:20:50 +01:00 |
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