mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity
3614 commits 122 branches 59 tags 73 MiB
Commit graph

3614 commits

This branch
This branch
All branches
Author SHA1 Message Date
whitequark
0515809448 synth_greenpak4: use attrmvcp to move LOC from wires to cells. 2016-08-10 20:09:35 +00:00
Clifford Wolf
e9fe57c75e Only allow posedge/negedge with 1 bit wide signals 2016-08-10 19:32:11 +02:00
Clifford Wolf
73b7232ec8 Fixed some compiler warnings in attrmap command 2016-08-10 13:44:08 +02:00
Clifford Wolf
b0aab4e304 Added "attrmap" command 2016-08-09 19:56:55 +02:00
Clifford Wolf
39da8eddae Added log_const() API 2016-08-09 19:56:10 +02:00
Clifford Wolf
3c6d31fd06 Added "attrmvcp" pass 2016-08-09 11:18:48 +02:00
Yury Gribov
f7730d43bb Use /proc/self/exe on Cygwin as well. 2016-08-08 12:00:27 +02:00
Clifford Wolf
9d15529214 Undo "preserve wire attributes in iopadmap" change (it was OK before) 2016-08-08 11:47:35 +02:00
Clifford Wolf
88a67afa7d Added "test_autotb -seed" (and "autotest.sh -S") 2016-08-06 13:32:29 +02:00
Clifford Wolf
90c17aad56 preserve wire attributes in iopadmap 2016-08-06 13:24:59 +02:00
Clifford Wolf
7f755dec75 Fixed bug in parsing real constants 2016-08-06 13:16:23 +02:00
Clifford Wolf
5d6765a9d2 Added "insbuf" command 2016-08-02 10:37:19 +02:00
Clifford Wolf
21e1bac084 Merge branch 'master' of github.com:cliffordwolf/yosys 2016-07-30 12:50:39 +02:00
Clifford Wolf
5fe13a16ea Added "write_verilog -defparam" 2016-07-30 12:46:06 +02:00
Clifford Wolf
7fa61cba1b Added "write_verilog -nodec -nostr" 2016-07-30 12:38:40 +02:00
Clifford Wolf
da56a5bbc6 Added $initstate support to smtbmc flow 2016-07-27 16:11:37 +02:00
Clifford Wolf
8d88fcb270 Added SatGen support for $anyconst 2016-07-27 15:52:20 +02:00
Clifford Wolf
9540be1d45 Removed $predict support from SatGen 2016-07-27 15:44:11 +02:00
Clifford Wolf
4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf
a7b0769623 Added "read_verilog -dump_rtlil" 2016-07-27 15:40:17 +02:00
Clifford Wolf
8537c4d206 Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() 2016-07-25 16:39:25 +02:00
Clifford Wolf
5b944ef11b Fixed a verilog parser memory leak 2016-07-25 16:37:58 +02:00
Clifford Wolf
7a67add95d Fixed parsing of empty positional cell ports 2016-07-25 12:48:03 +02:00
Clifford Wolf
b1c432af56 Improvements in CellEdgesDatabase 2016-07-24 17:21:53 +02:00
Clifford Wolf
f162b858f2 Added CellEdgesDatabase API 2016-07-24 13:59:57 +02:00
Clifford Wolf
54966679df Moved SatHelper::setup_init() code to SatHelper::setup() 2016-07-24 12:18:39 +02:00
Clifford Wolf
34e833103b Added $initstate support to "sat" command 2016-07-23 17:01:03 +02:00
Clifford Wolf
9aae1d1e8f No tristate warning message for "read_verilog -lib" 2016-07-23 11:56:53 +02:00
Clifford Wolf
89deb412c6 Added satgen initstate support 2016-07-22 10:28:45 +02:00
Clifford Wolf
7fef5ff104 Using $initstate in "initial assume" and "initial assert" 2016-07-21 14:37:28 +02:00
Clifford Wolf
5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf
b3155af5f6 Added examples/smtbmc 2016-07-13 09:49:05 +02:00
Clifford Wolf
2afc72cae3 Merge pull request #191 from whitequark/json-module-attributes 
write_json: also write module attributes
 2016-07-13 09:39:27 +02:00
Clifford Wolf
9e5c9471e3 Merge pull request #193 from azonenberg/master 
Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP
 2016-07-13 09:24:31 +02:00
Andrew Zonenberg
32bea97b75 Merge https://github.com/cliffordwolf/yosys 2016-07-12 16:12:37 -07:00
Clifford Wolf
e92998a79c Minor bugfix in FSM reset state detection 2016-07-12 09:46:15 +02:00
whitequark
546233f0e1 write_json: also write module attributes. 2016-07-12 06:32:04 +00:00
Andrew Zonenberg
52a738a544 Added GP_DAC cell 2016-07-11 22:45:55 -07:00
Andrew Zonenberg
baae472b83 Removed VOUT port of GP_BANDGAP 2016-07-11 22:45:42 -07:00
Andrew Zonenberg
8619d33114 Removed splitnets in prep for new gp4par parser 2016-07-11 22:42:25 -07:00
Clifford Wolf
c71785d65e Yosys-smtbmc: Support for hierarchical VCD dumping 2016-07-11 12:49:33 +02:00
Clifford Wolf
0153ad85d9 Moved smt2 yosys info parsing from smtbmc.py to smtio.py 2016-07-11 11:49:05 +02:00
Clifford Wolf
cdb58f68ab Added "prep -auto-top" and "synth -auto-top" 2016-07-11 11:40:55 +02:00
Clifford Wolf
a72fb85dc2 Merge branch 'master' of github.com:cliffordwolf/yosys 2016-07-10 18:17:09 +02:00
Clifford Wolf
307e31a95e Merge pull request #189 from whitequark/master 
greenpak4: add GP_COUNT{8,14}_ADV cells
 2016-07-10 18:12:00 +02:00
Clifford Wolf
771c5fe000 Support for hierarchical designs in smt2 back-end 2016-07-10 18:11:25 +02:00
whitequark
c0645839fe greenpak4: add GP_COUNT{8,14}_ADV cells. 2016-07-10 15:46:46 +00:00
Clifford Wolf
b5a9fba0db Further improved fsm_detect output, attempt to detect self-resetting circuits 2016-07-09 14:02:49 +02:00