Martin Povišer
04d2f55bec
fixup! add qlf_k6n10f architecture + bram inference
2023-11-27 18:28:10 +01:00
Martin Povišer
53bda484f8
quicklogic: Set initial values on inferred TDP36K
2023-11-27 17:43:21 +01:00
Martin Povišer
5bc587c843
quicklogic: Add k6n10f DSP test
2023-11-27 17:43:21 +01:00
Martin Povišer
03b45c883a
ql_dsp_io_regs: Fix ID strings, constant detection
2023-11-27 17:27:46 +01:00
Martin Povišer
502559cba4
quicklogic: Fix dffs.ys test
2023-11-27 17:27:46 +01:00
Martin Povišer
9d04201e86
synth_quicklogic: Fix missing FF mapping
2023-11-27 14:22:28 +01:00
Martin Povišer
3e004f7b13
quicklogic: Drop blackbox off adder_carry
2023-11-27 14:21:59 +01:00
Martin Povišer
a3b3333eeb
quicklogic: Add basic k6n10f tests
2023-11-27 12:14:48 +01:00
Martin Povišer
90f427c7a8
synth_quiclogic: Fix conditioning of bram passes
2023-11-27 12:05:55 +01:00
Martin Povišer
74296e3d92
quicklogic: Move pp3 tests one level down
2023-11-27 12:05:55 +01:00
Martin Povišer
f84ab98055
ql_dsp_macc: Tune DSP inference code
2023-11-27 12:05:55 +01:00
Martin Povišer
306e688406
ql_dsp_*: Clean up
...
Clean up the code up to Yosys standards. Drop detection of
QL_DSP2_MULTADD in io_regs since those cells can't be inferred with
the current flow anyway.
2023-11-27 12:05:55 +01:00
Martin Povišer
6d7dafe5e5
ql_k6n10f: Remove support for parameter-configured DSP variety
2023-11-27 12:05:55 +01:00
N. Engelhardt
a19ac1bbe1
merge brams_final_map.v into brams_map.v
2023-11-27 12:05:55 +01:00
N. Engelhardt
9ce53ea3e2
add dsp inference
2023-11-27 12:05:53 +01:00
N. Engelhardt
7c0dbc8822
change ql-bram-types pass to use mode parameter; clean up primitive libraries
2023-11-27 12:05:52 +01:00
N. Engelhardt
688455ef69
add qlf_k6n10f architecture + bram inference
...
(Copied from QuickLogic Yosys plugin repo)
2023-11-27 12:05:45 +01:00
N. Engelhardt
e230a871be
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-11-27 08:37:33 +01:00
github-actions[bot]
031ad38b5c
Bump version
2023-11-24 00:15:38 +00:00
Miodrag Milanović
5e603c2241
Merge pull request #4042 from YosysHQ/verific_cell
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Verific: Add attributes to module instantiation
2023-11-23 11:38:01 +01:00
Miodrag Milanovic
8f207eed1b
Add attributes to module instantiation
2023-11-23 11:01:49 +01:00
github-actions[bot]
c95298225d
Bump version
2023-11-21 00:16:08 +00:00
Martin Povišer
34f851f132
Merge pull request #4040 from povik/fmt-time
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fmt: Handle free-standing time arguments
2023-11-20 18:11:24 +01:00
Martin Povišer
282ce24eec
fmt: Handle free-standing time arguments
2023-11-20 17:25:42 +01:00
Jannis Harder
b23a607421
Merge pull request #4035 from jix/smtbmc-incremental
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smtbmc: Add --incremental mode
2023-11-20 17:00:29 +01:00
Miodrag Milanović
191ac91951
Merge pull request #4031 from nakengelhardt/nak/fix_vhdl_blackbox_nullptr
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verific: don't try to import attributes from nullptr
2023-11-20 15:37:01 +01:00
github-actions[bot]
ab6c1d368b
Bump version
2023-11-18 00:15:31 +00:00
N. Engelhardt
fa5fb811df
Merge pull request #4037 from YosysHQ/lofty/ice40-abc9-oopsie
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ice40: fix -noabc9
2023-11-17 14:36:16 +01:00
Lofty
5c96746309
ice40: fix -noabc9
2023-11-17 12:49:17 +00:00
Jannis Harder
e319606ec9
smtbmc: Add --incremental mode
2023-11-16 13:22:17 +01:00
N. Engelhardt
032fab1f54
Merge pull request #4032 from YosysHQ/lofty/gowin-abc9-oopsie
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gowin: fix typo
2023-11-15 11:07:49 +01:00
github-actions[bot]
7eea047793
Bump version
2023-11-15 00:15:49 +00:00
Lofty
309558767d
gowin: fix typo
2023-11-14 22:37:29 +00:00
N. Engelhardt
5fb1264db5
verific: don't try to import attributes from nullptr
2023-11-14 15:05:24 +01:00
Catherine
c11744b4ef
Fix WASI compilation flags for abc.
2023-11-14 03:33:35 +00:00
Catherine
726c501e7e
Update WASI compilation flags to include required libraries
2023-11-14 02:05:39 +00:00
github-actions[bot]
46408b5da3
Bump version
2023-11-14 00:15:32 +00:00
N. Engelhardt
8e470add4d
Merge pull request #4029 from YosysHQ/lofty/abc9-again
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ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 17:29:57 +01:00
N. Engelhardt
52d3fa6d77
Merge pull request #4022 from povik/machxo3-qor-work
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MachXO3 QoR improvements
2023-11-13 16:56:06 +01:00
N. Engelhardt
3fef81b537
Merge pull request #4028 from povik/cmp2softlogic
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synth_lattice: Optionally do constant comparisons in soft logic
2023-11-13 16:53:04 +01:00
Jannis Harder
6cf50d16a8
Merge pull request #3973 from anonkey/master
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cli(tcl): add ability to pass argument to tcl script from cli
2023-11-13 16:29:05 +01:00
Lofty
7ae4041e20
ice40, ecp5, gowin: enable ABC9 by default
2023-11-13 15:28:13 +00:00
N. Engelhardt
04083b4f15
Merge pull request #4027 from YosysHQ/achronix_typo
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Fix typo in help message (Acrhonix -> Achronix)
2023-11-13 16:04:24 +01:00
Martin Povišer
3ffa4b5e5d
synth_lattice: Wire up cmp2softlogic as an option
2023-11-13 10:42:12 +01:00
Martin Povišer
f7d4a855c6
techlibs: Add cmp2softlogic.v to common
2023-11-13 10:42:12 +01:00
Krystine Sherwin
83d2f4f334
techlibs: fix typo in help message
2023-11-13 16:29:52 +13:00
github-actions[bot]
5691cd0958
Bump version
2023-11-08 00:15:30 +00:00
Martin Povišer
fed2720999
synth_lattice: Optimize flip-flop memories better
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After `memory_map` maps memories to flip-flops we need to let `opt`
remove undef muxes, otherwise we block enable/reset signal inference by
`opt_dff` which is in detriment to QoR.
2023-11-07 16:29:56 +01:00
Martin Povišer
ee3a4ce14d
synth_lattice: Merge NOT gates on DFF control signals
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`dfflegalize` will emit NOT gates to drive control signals on flip-flops
when mapping to supported flip-flop polarities. Typically in a design
this will produce a number of NOT gates driven by the same signal. For
one reason or another ABC doesn't fully cancel this redundancy during
LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
QoR.
2023-11-07 16:21:39 +01:00
N. Engelhardt
63cec22a0c
Merge pull request #3883 from phsauter/peepopt-shiftadd
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peepopt: Add `shiftadd` pattern
2023-11-07 10:42:15 +01:00
