YRabbit
9d0bca9775
Gowin. Add an energy saving primitive
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We add a BANDGAP primitive used to turn off power to OSC, PLL and other
things on some GOWIN chips.
We also mark this primitive and GSR as keep.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2024-07-06 18:58:21 +10:00
N. Engelhardt
dac5bd1983
Merge pull request #4455 from phsauter/shiftadd-limit-padding
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peepopt: limit padding from shiftadd
2024-07-06 08:10:25 +02:00
Tony Min
6fe0e00050
Add missing u sram init ( #3 )
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add missing INIT for uSRAM
2024-07-04 16:39:10 -04:00
Tony Min
e9ff5f7d91
Merge pull request #2 from tony-min-1/move_tests
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Move tests
2024-07-04 16:05:04 -04:00
chunlin min
9de5602574
ininclude microchip tests in makefile
2024-07-04 15:54:59 -04:00
chunlin min
8e7ec2d660
add assertions for synth_microchip tests
2024-07-04 15:45:44 -04:00
chunlin min
e3c4791e5b
move microchip tests from techlibs/microchip/tests to tests/arch/microchip
2024-07-04 14:16:52 -04:00
chunlin min
19d3214861
use output reg instead of additional reg declaration
2024-07-04 14:13:26 -04:00
Tony Min
7ff8912338
Merge pull request #1 from tony-min-1/change_filenames
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changes made to filenames + references
2024-07-04 14:04:36 -04:00
C77874
5ba06fd947
another typo
2024-07-04 10:33:59 -07:00
C77874
6b80e02d62
missed a few pf instances
2024-07-04 10:25:15 -07:00
C77874
c385421c17
rename options
2024-07-04 09:45:04 -07:00
C77874
d0cd01adfe
fixed typos, build with makefile succeeds
2024-07-04 09:33:58 -07:00
C77874
59e45be275
Merge branch 'mchp' of https://github.com/tony-min-1/yosys into change_filenames
2024-07-04 09:00:38 -07:00
C77874
0bb7d1373f
changes made to filenames + references
2024-07-04 08:53:41 -07:00
Chun Lin Min
7770fa70e1
fix cells_sim.v
2024-07-04 05:20:22 -07:00
Chun Lin Min
e5bdc9b5c9
remove DSP48 references
2024-07-03 07:20:29 -07:00
Chun Lin Min
f57b624281
fix indent
2024-07-02 13:54:36 -07:00
Chun Lin Min
68a11c9941
more indent fix
2024-07-02 13:51:48 -07:00
Chun Lin Min
2ced2752e9
replace space indent with tab indent
2024-07-02 13:47:18 -07:00
Chun Lin Min
acddc36389
add PolarFire FPGA support
2024-07-02 12:44:30 -07:00
George Rennie
339d4e8932
hashlib: Correct prime sequence
2024-07-02 08:10:18 +01:00
George Rennie
78ae4ed9ac
hashlib: Add some more primes
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* Add some primes as suggested in #4458 . This allows larger hashtables
to be allocated for very big designs
2024-07-01 12:37:41 +01:00
github-actions[bot]
a739e21a5f
Bump version
2024-06-29 00:16:56 +00:00
Catherine
580aaa362d
opt_lut_ins: fix name of global object. NFCI
2024-06-28 15:12:36 +00:00
Martin Povišer
07daf61ae6
Merge pull request #4467 from povik/fix-add-shiftx
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rtlil: Fix `addShiftx` for signed shifts
2024-06-26 18:17:28 +02:00
Emil J. Tywoniak
01f332e750
opt_expr: reduce mostly harmless warning to log
2024-06-25 20:18:49 +02:00
github-actions[bot]
1288166f7a
Bump version
2024-06-25 00:17:11 +00:00
Miodrag Milanović
1e401c3e04
Merge pull request #4460 from YosysHQ/micko/c++17
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Make C++17 compiler required
2024-06-24 19:54:30 +02:00
Martin Povišer
fa4a2b6b0d
opt_expr: In clkinv loop ignore irrelevant cells early
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Each call to `handle_clkpol_celltype_swap` has a conversion of the
cell's type ID to an allocated string. This can sum up to a
non-negligible time being spent in the clkpol code even for a design
which doesn't have any flip-flop gates.
2024-06-24 18:32:33 +02:00
Martin Povišer
7a8a69b65c
opt_expr: Revisit sorting in replace_const_cells
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Avoid building a cell-to-inbit map when sorting the cells, add a warning
if we are unable to sort, and move the code treating non-combinational
cells ahead of the rest (this means we don't need to pass
non-combinational cells to the TopoSort object at all).
2024-06-24 18:32:33 +02:00
Miodrag Milanovic
777624ccf5
Make yosys-config dependant of Makefile
2024-06-24 16:08:08 +02:00
Martin Povišer
89d939334e
rtlil: Fix addShiftx for signed shifts
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Only the `B` input (the shift amount) can be marked as signed on a
`$shiftx` cell. Adapt the helper accordingly and prevent it from
creating invalid RTLIL when called with `is_signed` set. Previously
it would mark both `A` and `B` as signed.
2024-06-21 15:14:08 +02:00
github-actions[bot]
6c8ae44ae7
Bump version
2024-06-20 00:17:08 +00:00
gatecat
22d8df1e7e
liberty: Support for IO liberty files for verification
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Signed-off-by: gatecat <gatecat@ds0.me>
2024-06-19 21:12:42 +02:00
github-actions[bot]
ede3750a6c
Bump version
2024-06-19 00:17:13 +00:00
Miodrag Milanović
8024688b1d
Merge pull request #4459 from YosysHQ/micko/vanilla_verific
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Verific build support improvements
2024-06-18 10:50:20 +02:00
Miodrag Milanovic
2bbf3112d9
Update VS build to C++17 build
2024-06-17 17:29:20 +02:00
Martin Povišer
f9b7b8fff0
Update documentation for C++17 switch
2024-06-17 17:08:13 +02:00
Miodrag Milanovic
141a2e3638
Make C++17 compiler required
2024-06-17 16:55:36 +02:00
Miodrag Milanovic
dfde792288
Refactored import code
2024-06-17 14:49:58 +02:00
Miodrag Milanovic
19da7f7d59
Update makefile to make options uniform
2024-06-17 13:29:11 +02:00
Miodrag Milanovic
0f3f731254
Handle -work for vhdl, and clean messages
2024-06-17 13:29:11 +02:00
Miodrag Milanovic
0a81c8e161
Import all modules from all libraries when when needed
2024-06-17 13:29:11 +02:00
Miodrag Milanovic
7c3094633d
Compile with hier_tree separate SV and VHDL as well
2024-06-17 13:29:11 +02:00
Miodrag Milanovic
e2e189647f
Cleanup
2024-06-17 13:29:11 +02:00
Miodrag Milanovic
7bec332b68
SV + VHDL with RTL support
2024-06-17 13:29:11 +02:00
Miodrag Milanovic
25d50bb2af
VHDL only build support
2024-06-17 13:29:11 +02:00
Miodrag Milanovic
54bf9ccf06
Add initial support for Verific without additional YosysHQ patch
2024-06-17 13:29:11 +02:00
Philippe Sauter
2f0f10cb87
peepopt: limit padding from shiftadd
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The input to a shift operation is padded.
This reduced the final number of MUX cells
but during techmap it can create huge
temporary multiplexers in the log shifter.
This significantly increases runtime and resources.
A limit is added with a warning when it is used.
2024-06-14 15:33:03 +02:00
